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| author | Richard Osborne <richard@xmos.com> | 2008-12-03 10:59:16 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2008-12-03 10:59:16 +0000 |
| commit | 269bc0042fc976b13b44c97c6546b4d726073940 (patch) | |
| tree | c0ac281b4ccbd9c9fe6978e5f2495a160e7c3561 /lib/Target/XCore | |
| parent | 370e5340a585d7d4b98bd855e52e4624c44ad681 (diff) | |
| download | external_llvm-269bc0042fc976b13b44c97c6546b4d726073940.zip external_llvm-269bc0042fc976b13b44c97c6546b4d726073940.tar.gz external_llvm-269bc0042fc976b13b44c97c6546b4d726073940.tar.bz2 | |
Add support for ISD::TRAP to the XCore backend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60479 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore')
| -rw-r--r-- | lib/Target/XCore/XCoreISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 15 |
2 files changed, 16 insertions, 1 deletions
diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index e24b998..e2d2ab7 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -106,6 +106,8 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) setOperationAction(ISD::ROTL , MVT::i32, Expand); setOperationAction(ISD::ROTR , MVT::i32, Expand); + setOperationAction(ISD::TRAP, MVT::Other, Legal); + // Expand jump tables for now setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::JumpTable, MVT::i32, Custom); diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 031ad87..4ee1f63 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -762,7 +762,7 @@ def CLZ_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src), // One operand short // TODO edu, eeu, waitet, waitef, freer, tstart, msync, mjoin, syncr, clrtp -// bru, setdp, setcp, setv, setev, kcall, ecallt, ecallf +// bru, setdp, setcp, setv, setev, kcall // dgetreg let isBranch=1, isIndirectBranch=1, isTerminator=1 in def BAU_1r : _F1R<(outs), (ins GRRegs:$addr), @@ -774,6 +774,16 @@ def SETSP_1r : _F1R<(outs), (ins GRRegs:$src), "set sp, $src", []>; +let isBarrier = 1, hasCtrlDep = 1 in +def ECALLT_1r : _F1R<(outs), (ins GRRegs:$src), + "ecallt $src", + []>; + +let isBarrier = 1, hasCtrlDep = 1 in +def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src), + "ecallf $src", + []>; + let isCall=1, // All calls clobber the the link register and the non-callee-saved registers: Defs = [R0, R1, R2, R3, R11, LR] in { @@ -852,6 +862,9 @@ def : Pat<(store GRRegs:$val, GRRegs:$addr), /// cttz def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>; +/// trap +def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>; + /// /// branch patterns /// |