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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-04-05 03:10:20 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-04-05 03:10:20 +0000 |
| commit | 4f8ea2957aa89b58fe484ab898ece009d2378173 (patch) | |
| tree | fdfe17e6a728d6560f0217760d6e3dd80ca924ed /lib/Target/XCore | |
| parent | 3c00f8936502465d080aa1a79a3b51d0fb89820c (diff) | |
| download | external_llvm-4f8ea2957aa89b58fe484ab898ece009d2378173.zip external_llvm-4f8ea2957aa89b58fe484ab898ece009d2378173.tar.gz external_llvm-4f8ea2957aa89b58fe484ab898ece009d2378173.tar.bz2 | |
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore')
| -rw-r--r-- | lib/Target/XCore/XCore.td | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/lib/Target/XCore/XCore.td b/lib/Target/XCore/XCore.td index b07445d..3840189 100644 --- a/lib/Target/XCore/XCore.td +++ b/lib/Target/XCore/XCore.td @@ -24,10 +24,7 @@ include "XCoreRegisterInfo.td" include "XCoreInstrInfo.td" include "XCoreCallingConv.td" -def XCoreInstrInfo : InstrInfo { - let TSFlagsFields = []; - let TSFlagsShifts = []; -} +def XCoreInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // XCore processors supported. |
