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authorRichard Osborne <richard@xmos.com>2010-03-10 13:27:10 +0000
committerRichard Osborne <richard@xmos.com>2010-03-10 13:27:10 +0000
commita2cc0613d05f9545947478942811c04f27601649 (patch)
treec70323bab4a06d239bfa9e18662a78af14580504 /lib/Target/XCore
parenta7e78402b8b3d3583e7b63fcca99a4034a2f4db4 (diff)
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Prefer LMUL to MACCU as LMUL has no tied operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98153 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore')
-rw-r--r--lib/Target/XCore/XCoreISelDAGToDAG.cpp6
-rw-r--r--lib/Target/XCore/XCoreISelLowering.cpp7
-rw-r--r--lib/Target/XCore/XCoreISelLowering.h3
3 files changed, 13 insertions, 3 deletions
diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
index 12967d4..29a6ab7 100644
--- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -220,6 +220,12 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
return CurDAG->getMachineNode(XCore::MACCS_l4r, dl, MVT::i32, MVT::i32,
Ops, 4);
}
+ case XCoreISD::LMUL: {
+ SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
+ N->getOperand(2), N->getOperand(3) };
+ return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
+ Ops, 4);
+ }
// Other cases are autogenerated.
}
}
diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp
index 70ceadd..d27adf4 100644
--- a/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/lib/Target/XCore/XCoreISelLowering.cpp
@@ -54,6 +54,7 @@ getTargetNodeName(unsigned Opcode) const
case XCoreISD::RETSP : return "XCoreISD::RETSP";
case XCoreISD::LADD : return "XCoreISD::LADD";
case XCoreISD::LSUB : return "XCoreISD::LSUB";
+ case XCoreISD::LMUL : return "XCoreISD::LMUL";
case XCoreISD::MACCU : return "XCoreISD::MACCU";
case XCoreISD::MACCS : return "XCoreISD::MACCS";
case XCoreISD::BR_JT : return "XCoreISD::BR_JT";
@@ -573,9 +574,9 @@ LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG)
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
SDValue Zero = DAG.getConstant(0, MVT::i32);
- SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
- DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
- LHS, RHS);
+ SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
+ DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
+ Zero, Zero);
SDValue Lo(Hi.getNode(), 1);
SDValue Ops[] = { Lo, Hi };
return DAG.getMergeValues(Ops, 2, dl);
diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h
index 6b467c3..6928138 100644
--- a/lib/Target/XCore/XCoreISelLowering.h
+++ b/lib/Target/XCore/XCoreISelLowering.h
@@ -54,6 +54,9 @@ namespace llvm {
// Corresponds to LSUB instruction
LSUB,
+ // Corresponds to LMUL instruction
+ LMUL,
+
// Corresponds to MACCU instruction
MACCU,