diff options
author | Eric Christopher <echristo@apple.com> | 2011-06-29 17:53:29 +0000 |
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committer | Eric Christopher <echristo@apple.com> | 2011-06-29 17:53:29 +0000 |
commit | ca42299619cf47371a42c2bda87d067e003657ea (patch) | |
tree | b931a51acdcd1d718efdcb3d93dec46b10f057dd /lib/Target/XCore | |
parent | d176af8cf3e3b3fb39385798e25e55449933648c (diff) | |
download | external_llvm-ca42299619cf47371a42c2bda87d067e003657ea.zip external_llvm-ca42299619cf47371a42c2bda87d067e003657ea.tar.gz external_llvm-ca42299619cf47371a42c2bda87d067e003657ea.tar.bz2 |
Move XCore from getRegClassForInlineAsmConstraint to
getRegForInlineAsmConstraint.
Part of rdar://9643582
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134080 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore')
-rw-r--r-- | lib/Target/XCore/XCoreISelLowering.cpp | 25 | ||||
-rw-r--r-- | lib/Target/XCore/XCoreISelLowering.h | 6 |
2 files changed, 14 insertions, 17 deletions
diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 8cabbbf..6d040e0 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -1591,21 +1591,18 @@ XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, // XCore Inline Assembly Support //===----------------------------------------------------------------------===// -std::vector<unsigned> XCoreTargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const -{ - if (Constraint.size() != 1) - return std::vector<unsigned>(); - - switch (Constraint[0]) { +std::pair<unsigned, const TargetRegisterClass*> +XCoreTargetLowering:: +getRegForInlineAsmConstraint(const std::string &Constraint, + EVT VT) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { default : break; case 'r': - return make_vector<unsigned>(XCore::R0, XCore::R1, XCore::R2, - XCore::R3, XCore::R4, XCore::R5, - XCore::R6, XCore::R7, XCore::R8, - XCore::R9, XCore::R10, XCore::R11, 0); - break; + return std::make_pair(0U, XCore::GRRegsRegisterClass); + } } - return std::vector<unsigned>(); + // Use the default implementation in TargetLowering to convert the register + // constraint into a member of a register class. + return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); } diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h index a8d67d4..9c803be 100644 --- a/lib/Target/XCore/XCoreISelLowering.h +++ b/lib/Target/XCore/XCoreISelLowering.h @@ -148,9 +148,9 @@ namespace llvm { SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; // Inline asm support - std::vector<unsigned> - getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; + std::pair<unsigned, const TargetRegisterClass*> + getRegForInlineAsmConstraint(const std::string &Constraint, + EVT VT) const; // Expand specifics SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const; |