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author | Nadav Rotem <nrotem@apple.com> | 2012-10-10 22:04:55 +0000 |
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committer | Nadav Rotem <nrotem@apple.com> | 2012-10-10 22:04:55 +0000 |
commit | e3d0e86919730784faaddcb5d9b0257c39b0804b (patch) | |
tree | 8cf4557c9fc5e5995d10657912b0c7c426e85ed2 /lib/Target/XCore | |
parent | 3a55b64e5e9d9586ece5918648b298c11b378d85 (diff) | |
download | external_llvm-e3d0e86919730784faaddcb5d9b0257c39b0804b.zip external_llvm-e3d0e86919730784faaddcb5d9b0257c39b0804b.tar.gz external_llvm-e3d0e86919730784faaddcb5d9b0257c39b0804b.tar.bz2 |
Add a new interface to allow IR-level passes to access codegen-specific information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165665 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore')
-rw-r--r-- | lib/Target/XCore/XCoreTargetMachine.cpp | 2 | ||||
-rw-r--r-- | lib/Target/XCore/XCoreTargetMachine.h | 9 |
2 files changed, 10 insertions, 1 deletions
diff --git a/lib/Target/XCore/XCoreTargetMachine.cpp b/lib/Target/XCore/XCoreTargetMachine.cpp index c71d978..0b7e3e1 100644 --- a/lib/Target/XCore/XCoreTargetMachine.cpp +++ b/lib/Target/XCore/XCoreTargetMachine.cpp @@ -32,7 +32,7 @@ XCoreTargetMachine::XCoreTargetMachine(const Target &T, StringRef TT, InstrInfo(), FrameLowering(Subtarget), TLInfo(*this), - TSInfo(*this) { + TSInfo(*this), STTI(&TLInfo) { } namespace { diff --git a/lib/Target/XCore/XCoreTargetMachine.h b/lib/Target/XCore/XCoreTargetMachine.h index f7fec29..c60c6a3 100644 --- a/lib/Target/XCore/XCoreTargetMachine.h +++ b/lib/Target/XCore/XCoreTargetMachine.h @@ -20,6 +20,7 @@ #include "XCoreISelLowering.h" #include "XCoreSelectionDAGInfo.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetTransformImpl.h" #include "llvm/DataLayout.h" namespace llvm { @@ -31,6 +32,8 @@ class XCoreTargetMachine : public LLVMTargetMachine { XCoreFrameLowering FrameLowering; XCoreTargetLowering TLInfo; XCoreSelectionDAGInfo TSInfo; + ScalarTargetTransformImpl STTI; + VectorTargetTransformImpl VTTI; public: XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, @@ -53,6 +56,12 @@ public: virtual const TargetRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } + virtual const ScalarTargetTransformInfo *getScalarTargetTransformInfo()const { + return &STTI; + } + virtual const VectorTargetTransformInfo *getVectorTargetTransformInfo()const { + return &VTTI; + } virtual const DataLayout *getDataLayout() const { return &DL; } // Pass Pipeline Configuration |