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| author | Tanya Lattner <tonic@nondot.org> | 2011-04-07 15:24:20 +0000 |
|---|---|---|
| committer | Tanya Lattner <tonic@nondot.org> | 2011-04-07 15:24:20 +0000 |
| commit | 0433b21c989e7d4817574b950387355fe05f59b5 (patch) | |
| tree | 6575a62e88e7e323f38ca9560685aa16677ed3e0 /lib/Target | |
| parent | 71001c97c6dda3df509ba4b9b37f979ea1aa8127 (diff) | |
| download | external_llvm-0433b21c989e7d4817574b950387355fe05f59b5.zip external_llvm-0433b21c989e7d4817574b950387355fe05f59b5.tar.gz external_llvm-0433b21c989e7d4817574b950387355fe05f59b5.tar.bz2 | |
Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index d030f68..330a781 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -5390,6 +5390,9 @@ static SDValue PerformANDCombine(SDNode *N, EVT VT = N->getValueType(0); SelectionDAG &DAG = DCI.DAG; + if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) + return SDValue(); + APInt SplatBits, SplatUndef; unsigned SplatBitSize; bool HasAnyUndefs; @@ -5423,6 +5426,9 @@ static SDValue PerformORCombine(SDNode *N, EVT VT = N->getValueType(0); SelectionDAG &DAG = DCI.DAG; + if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) + return SDValue(); + APInt SplatBits, SplatUndef; unsigned SplatBitSize; bool HasAnyUndefs; |