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authorNate Begeman <natebegeman@mac.com>2008-02-14 07:25:46 +0000
committerNate Begeman <natebegeman@mac.com>2008-02-14 07:25:46 +0000
commit0fec975a183002d9bf59a4c224c048ef9dfd0ba2 (patch)
tree7a8d9a374762bd382abd208efe77f8465f75b397 /lib/Target
parentf504eefb6e5bdd72d59dff605719cdae53919ebf (diff)
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Move some useful operands up into the all-targets .td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47115 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/CellSPU/SPUOperands.td3
-rw-r--r--lib/Target/Target.td3
2 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/CellSPU/SPUOperands.td b/lib/Target/CellSPU/SPUOperands.td
index 2a3551d..79d1a7a 100644
--- a/lib/Target/CellSPU/SPUOperands.td
+++ b/lib/Target/CellSPU/SPUOperands.td
@@ -538,9 +538,6 @@ def rotNeg7imm_i16 : Operand<i16> {
let PrintMethod = "printROTNeg7Imm";
}
-// Floating point immediate operands
-def f32imm : Operand<f32>;
-
def target : Operand<OtherVT> {
let PrintMethod = "printBranchOperand";
}
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index a2669dc..f8fa719 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -277,6 +277,9 @@ def i16imm : Operand<i16>;
def i32imm : Operand<i32>;
def i64imm : Operand<i64>;
+def f32imm : Operand<f32>;
+def f64imm : Operand<f64>;
+
/// zero_reg definition - Special node to stand for the zero register.
///
def zero_reg;