MachineInstr::getOpCode() --> getOpcode() in SPARC back-end.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11335 91177308-0d34-0410-b5e6-96231b3b80d8

10 files changed, 41 insertions, 41 deletions

diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
index e8b8785..131107b 100644
--- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
@@ -129,7 +129,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
 {
   std::vector<MachineInstr*> MVec;
   
-  MachineOpCode opCode = minstr->getOpCode();
+  MachineOpCode opCode = minstr->getOpcode();
   const TargetInstrInfo& instrInfo = target.getInstrInfo();
   int resultPos = instrInfo.getResultPos(opCode);
   int immedPos = instrInfo.getImmedConstantPos(opCode);
diff --git a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
index be09e62..d8878ad 100644
--- a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
+++ b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp
@@ -78,7 +78,7 @@ void BBLiveVar::calcDefUseSets() {
         // Put Phi operands in UseSet for the incoming edge, not node.
         // They must not "hide" later defs, and must be handled specially
         // during set propagation over the CFG.
-	if (MI->getOpCode() == V9::PHI) {         // for a phi node
+	if (MI->getOpcode() == V9::PHI) {         // for a phi node
           const Value *ArgVal = Op;
 	  const BasicBlock *PredBB = cast<BasicBlock>(*++OpI); // next ptr is BB
 	  
@@ -97,7 +97,7 @@ void BBLiveVar::calcDefUseSets() {
 
     // do for implicit operands as well
     for (unsigned i = 0; i < MI->getNumImplicitRefs(); ++i) {
-      assert(MI->getOpCode() != V9::PHI && "Phi cannot have implicit operands");
+      assert(MI->getOpcode() != V9::PHI && "Phi cannot have implicit operands");
       const Value *Op = MI->getImplicitRef(i);
 
       if (Op->getType() == Type::LabelTy)             // don't process labels
diff --git a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
index e342760..fd23a23 100644
--- a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
+++ b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp
@@ -295,12 +295,12 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) {
     // If the current machine instruction has delay slots, mark values
     // used by this instruction as live before and after each delay slot
     // instruction (After(MI) is the same as Before(MI+1) except for last MI).
-    if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(MI->getOpCode())) {
+    if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(MI->getOpcode())) {
       MachineBasicBlock::const_iterator fwdMII = MII.base(); // ptr to *next* MI
       for (unsigned i = 0; i < DS; ++i, ++fwdMII) {
         assert(fwdMII != MIVec.end() && "Missing instruction in delay slot?");
         MachineInstr* DelaySlotMI = *fwdMII;
-        if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpCode())) {
+        if (! TM.getInstrInfo().isNop(DelaySlotMI->getOpcode())) {
           set_union(*MInst2LVSetBI[DelaySlotMI], *NewSet);
           if (i+1 == DS)
             set_union(*MInst2LVSetAI[DelaySlotMI], *NewSet);
diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
index 3806804..2c0196d 100644
--- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
@@ -176,8 +176,8 @@ void LiveRangeInfo::constructLiveRanges() {
       // If the machine instruction is a  call/return instruction, add it to
       // CallRetInstrList for processing its args, ret value, and ret addr.
       // 
-      if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
-	 TM.getInstrInfo().isCall(MInst->getOpCode()))
+      if(TM.getInstrInfo().isReturn(MInst->getOpcode()) ||
+	 TM.getInstrInfo().isCall(MInst->getOpcode()))
 	CallRetInstrList.push_back(MInst); 
  
       // iterate over explicit MI operands and create a new LR
@@ -243,7 +243,7 @@ void LiveRangeInfo::suggestRegs4CallRets() {
   std::vector<MachineInstr*>::iterator It = CallRetInstrList.begin();
   for( ; It != CallRetInstrList.end(); ++It) {
     MachineInstr *MInst = *It;
-    MachineOpCode OpCode = MInst->getOpCode();
+    MachineOpCode OpCode = MInst->getOpcode();
 
     if ((TM.getInstrInfo()).isReturn(OpCode))
       MRI.suggestReg4RetValue(MInst, *this);
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 0f1f6d2..e45f13b 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -237,7 +237,7 @@ void PhyRegAlloc::buildInterferenceGraphs() {
 
       // get the LV set after the instruction
       const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
-      bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
+      bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpcode());
 
       if (isCallInst) {
 	// set the isCallInterference flag of each live range which extends
@@ -262,7 +262,7 @@ void PhyRegAlloc::buildInterferenceGraphs() {
       // another.  This must be done because pseudo-instructions may be
       // expanded to multiple instructions by the assembler, so all the
       // operands must get distinct registers.
-      if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
+      if (TM.getInstrInfo().isPseudoInstr(MInst->getOpcode()))
       	addInterf4PseudoInstr(MInst);
 
       // Also add interference for any implicit definitions in a machine
@@ -443,7 +443,7 @@ bool PhyRegAlloc::markAllocatedRegs(MachineInstr* MInst)
 void PhyRegAlloc::updateInstruction(MachineBasicBlock::iterator& MII,
                                     MachineBasicBlock &MBB) {
   MachineInstr* MInst = *MII;
-  unsigned Opcode = MInst->getOpCode();
+  unsigned Opcode = MInst->getOpcode();
 
   // Reset tmp stack positions so they can be reused for each machine instr.
   MF->getInfo()->popAllTempValues();  
@@ -506,7 +506,7 @@ void PhyRegAlloc::updateMachineCode()
     // their assigned registers or insert spill code, as appropriate. 
     // Also, fix operands of call/return instructions.
     for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
-      if (! TM.getInstrInfo().isDummyPhiInstr((*MII)->getOpCode()))
+      if (! TM.getInstrInfo().isDummyPhiInstr((*MII)->getOpcode()))
         updateInstruction(MII, MBB);
 
     // Now, move code out of delay slots of branches and returns if needed.
@@ -526,14 +526,14 @@ void PhyRegAlloc::updateMachineCode()
     for (MachineBasicBlock::iterator MII = MBB.begin();
          MII != MBB.end(); ++MII)
       if (unsigned delaySlots =
-          TM.getInstrInfo().getNumDelaySlots((*MII)->getOpCode())) { 
+          TM.getInstrInfo().getNumDelaySlots((*MII)->getOpcode())) { 
           MachineInstr *MInst = *MII, *DelaySlotMI = *(MII+1);
           
           // Check the 2 conditions above:
           // (1) Does a branch need instructions added after it?
           // (2) O/w does delay slot instr. need instrns before or after?
-          bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpCode()) ||
-                           TM.getInstrInfo().isReturn(MInst->getOpCode()));
+          bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpcode()) ||
+                           TM.getInstrInfo().isReturn(MInst->getOpcode()));
           bool cond1 = (isBranch &&
                         AddedInstrMap.count(MInst) &&
                         AddedInstrMap[MInst].InstrnsAfter.size() > 0);
@@ -575,7 +575,7 @@ void PhyRegAlloc::updateMachineCode()
       MachineInstr *MInst = *MII; 
 
       // do not process Phis
-      if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpCode()))
+      if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpcode()))
 	continue;
 
       // if there are any added instructions...
@@ -583,11 +583,11 @@ void PhyRegAlloc::updateMachineCode()
         AddedInstrns &CallAI = AddedInstrMap[MInst];
 
 #ifndef NDEBUG
-        bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpCode()) ||
-                         TM.getInstrInfo().isReturn(MInst->getOpCode()));
+        bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpcode()) ||
+                         TM.getInstrInfo().isReturn(MInst->getOpcode()));
         assert((!isBranch ||
                 AddedInstrMap[MInst].InstrnsAfter.size() <=
-                TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) &&
+                TM.getInstrInfo().getNumDelaySlots(MInst->getOpcode())) &&
                "Cannot put more than #delaySlots instrns after "
                "branch or return! Need to handle temps differently.");
 #endif
@@ -638,9 +638,9 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
   MachineInstr *MInst = *MII;
   const BasicBlock *BB = MBB.getBasicBlock();
 
-  assert((! TM.getInstrInfo().isCall(MInst->getOpCode()) || OpNum == 0) &&
+  assert((! TM.getInstrInfo().isCall(MInst->getOpcode()) || OpNum == 0) &&
          "Outgoing arg of a call must be handled elsewhere (func arg ok)");
-  assert(! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
+  assert(! TM.getInstrInfo().isReturn(MInst->getOpcode()) &&
 	 "Return value of a ret must be handled elsewhere");
 
   MachineOperand& Op = MInst->getOperand(OpNum);
@@ -659,7 +659,7 @@ void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
   // trample those!  Verify that the set is included in the LV set before MInst.
   if (MII != MBB.begin()) {
     MachineInstr *PredMI = *(MII-1);
-    if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpCode()))
+    if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpcode()))
       assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
              .empty() && "Live-var set before branch should be included in "
              "live-var set of each delay slot instruction!");
@@ -745,7 +745,7 @@ PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
                                     std::vector<MachineInstr*> &instrnsAfter,
                                     MachineInstr *CallMI, 
                                     const BasicBlock *BB) {
-  assert(TM.getInstrInfo().isCall(CallMI->getOpCode()));
+  assert(TM.getInstrInfo().isCall(CallMI->getOpcode()));
   
   // hash set to record which registers were saved/restored
   hash_set<unsigned> PushedRegSet;
diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
index 277da69..af86e05 100644
--- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
+++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
@@ -566,7 +566,7 @@ namespace {
 inline bool
 SparcAsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
                                        unsigned int opNum) {
-  switch (MI->getOpCode()) {
+  switch (MI->getOpcode()) {
   case V9::JMPLCALLr:
   case V9::JMPLCALLi:
   case V9::JMPLRETr:
@@ -580,9 +580,9 @@ SparcAsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
 inline bool
 SparcAsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
                                        unsigned int opNum) {
-  if (Target.getInstrInfo().isLoad(MI->getOpCode()))
+  if (Target.getInstrInfo().isLoad(MI->getOpcode()))
     return (opNum == 0);
-  else if (Target.getInstrInfo().isStore(MI->getOpCode()))
+  else if (Target.getInstrInfo().isStore(MI->getOpcode()))
     return (opNum == 1);
   else
     return false;
@@ -601,15 +601,15 @@ SparcAsmPrinter::printOperands(const MachineInstr *MI,
   const MachineOperand& mop = MI->getOperand(opNum);
   
   if (OpIsBranchTargetLabel(MI, opNum)) {
-    PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpCode());
+    PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpcode());
     return 2;
   } else if (OpIsMemoryAddressBase(MI, opNum)) {
     toAsm << "[";
-    PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpCode());
+    PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpcode());
     toAsm << "]";
     return 2;
   } else {
-    printOneOperand(mop, MI->getOpCode());
+    printOneOperand(mop, MI->getOpcode());
     return 1;
   }
 }
@@ -691,7 +691,7 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
 }
 
 void SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) {
-  unsigned Opcode = MI->getOpCode();
+  unsigned Opcode = MI->getOpcode();
 
   if (Target.getInstrInfo().isDummyPhiInstr(Opcode))
     return;  // IGNORE PHI NODES
diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp
index 5b729ec..25c5fde 100644
--- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp
@@ -874,7 +874,7 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
   if (firstNewInstr < mvec.size()) {
     cost = 0;
     for (unsigned i=firstNewInstr; i < mvec.size(); ++i)
-      cost += target.getInstrInfo().minLatency(mvec[i]->getOpCode());
+      cost += target.getInstrInfo().minLatency(mvec[i]->getOpcode());
   }
   
   return cost;
@@ -1918,7 +1918,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
           const MachineCodeForInstruction& mcfi =
             MachineCodeForInstruction::get(
                 cast<InstructionNode>(subtreeRoot->parent())->getInstruction());
-          if (mcfi.size() == 0 || mcfi.front()->getOpCode() == V9::FSMULD)
+          if (mcfi.size() == 0 || mcfi.front()->getOpcode() == V9::FSMULD)
             forwardOperandNum = 0;    // forward first operand to user
         }
 
diff --git a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
index 0f68863..60c7bcb 100644
--- a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
+++ b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
@@ -32,7 +32,7 @@ DeleteInstruction(MachineBasicBlock& mvec,
   if (BBI != mvec.begin()) {
       const TargetInstrInfo& mii = target.getInstrInfo();
       MachineInstr* predMI = *(BBI-1);
-      if (unsigned ndelay = mii.getNumDelaySlots(predMI->getOpCode())) {
+      if (unsigned ndelay = mii.getNumDelaySlots(predMI->getOpcode())) {
         // This instruction is in a delay slot of its predecessor, so
         // replace it with a nop. By replacing in place, we save having
         // to update the I-I maps.
@@ -61,12 +61,12 @@ DeleteInstruction(MachineBasicBlock& mvec,
 //----------------------------------------------------------------------------
 
 static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
-  if (MI->getOpCode() == V9::FMOVS || MI->getOpCode() == V9::FMOVD) {
+  if (MI->getOpcode() == V9::FMOVS || MI->getOpcode() == V9::FMOVD) {
     return (// both operands are allocated to the same register
             MI->getOperand(0).getAllocatedRegNum() == 
             MI->getOperand(1).getAllocatedRegNum());
-  } else if (MI->getOpCode() == V9::ADDr || MI->getOpCode() == V9::ORr ||
-             MI->getOpCode() == V9::ADDi || MI->getOpCode() == V9::ORi) {
+  } else if (MI->getOpcode() == V9::ADDr || MI->getOpcode() == V9::ORr ||
+             MI->getOpcode() == V9::ADDi || MI->getOpcode() == V9::ORi) {
     unsigned srcWithDestReg;
     
     for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)
diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
index 323d0cf..4398f6b 100644
--- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
+++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
@@ -155,7 +155,7 @@ void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
       
       // Remove the NOPs in the delay slots of the return instruction
       unsigned numNOPs = 0;
-      while (termMvec.back()->getOpCode() == V9::NOP)
+      while (termMvec.back()->getOpcode() == V9::NOP)
       {
         assert( termMvec.back() == MBB.back());
         delete MBB.pop_back();
@@ -166,7 +166,7 @@ void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
         
       // Check that we found the right number of NOPs and have the right
       // number of instructions to replace them.
-      unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpCode());
+      unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpcode());
       assert(numNOPs == ndelays && "Missing NOPs in delay slots?");
       assert(ndelays == 1 && "Cannot use epilog code for delay slots?");
         
diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index 85eb3bc..5033a0a 100644
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -312,7 +312,7 @@ unsigned SparcRegInfo::getRegClassIDOfRegType(int regType) const {
 void SparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI, 
 					   LiveRangeInfo& LRI) const {
 
-  assert(target.getInstrInfo().isReturn(RetMI->getOpCode()));
+  assert(target.getInstrInfo().isReturn(RetMI->getOpcode()));
   
   // return address is always mapped to i7 so set it immediately
   RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
@@ -570,7 +570,7 @@ void SparcRegInfo::colorMethodArgs(const Function *Meth,
 //---------------------------------------------------------------------------
 void SparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI, 
 					     LiveRangeInfo& LRI) const {
-  assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
+  assert ( (target.getInstrInfo()).isCall(CallMI->getOpcode()) );
 
   CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI); 
   
@@ -639,7 +639,7 @@ void SparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
 void SparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI, 
                                             LiveRangeInfo& LRI) const {
 
-  assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) );
+  assert( (target.getInstrInfo()).isReturn( RetMI->getOpcode() ) );
 
   suggestReg4RetAddr(RetMI, LRI);