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author | Bill Wendling <isanbard@gmail.com> | 2008-05-30 06:47:04 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2008-05-30 06:47:04 +0000 |
commit | 12e97211a2b0c22b38041f2be1b29c8e3a19c44a (patch) | |
tree | ac73e70aa386b1c40d3973547f6629b4b0b3fcd1 /lib/Target | |
parent | a5bdf6e2d1af7db6ddcc1f5fbf7a53d61c7151ce (diff) | |
download | external_llvm-12e97211a2b0c22b38041f2be1b29c8e3a19c44a.zip external_llvm-12e97211a2b0c22b38041f2be1b29c8e3a19c44a.tar.gz external_llvm-12e97211a2b0c22b38041f2be1b29c8e3a19c44a.tar.bz2 |
Add the "AsCheapAsAMove" flag to some 64-bit xor instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51761 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/X86/X86Instr64bit.td | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index de422f0..382a27c 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -751,7 +751,7 @@ def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src), [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst)]>; let isTwoAddress = 1 in { -let isCommutable = 1 in +let isCommutable = 1, isAsCheapAsAMove = 1 in def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), "xor{q}\t{$src2, $dst|$dst, $src2}", [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>; @@ -1091,7 +1091,8 @@ def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src) // FIXME: remove when we can teach regalloc that xor reg, reg is ok. // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove // when we have a better way to specify isel priority. -let Defs = [EFLAGS], AddedComplexity = 1, isReMaterializable = 1 in +let Defs = [EFLAGS], AddedComplexity = 1, + isReMaterializable = 1, isAsCheapAsAMove = 1 in def MOV64r0 : RI<0x31, MRMInitReg, (outs GR64:$dst), (ins), "xor{l}\t${dst:subreg32}, ${dst:subreg32}", [(set GR64:$dst, 0)]>; |