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| author | Nate Begeman <natebegeman@mac.com> | 2008-08-11 17:36:31 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2008-08-11 17:36:31 +0000 |
| commit | 1db3c92306f551a81440dffd88ce07b9fbea97f4 (patch) | |
| tree | 0aba14c45ea862a4d6a15e416cdb5a15aee0f261 /lib/Target | |
| parent | 1e7f7865ebd3b47c93dc8867abe5baae0df0ebce (diff) | |
| download | external_llvm-1db3c92306f551a81440dffd88ce07b9fbea97f4.zip external_llvm-1db3c92306f551a81440dffd88ce07b9fbea97f4.tar.gz external_llvm-1db3c92306f551a81440dffd88ce07b9fbea97f4.tar.bz2 | |
Implement ISD::TRAP support on PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54644 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 11 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 3 | ||||
| -rw-r--r-- | lib/Target/PowerPC/README.txt | 1 |
4 files changed, 18 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index fcf235c..2dec8d6 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -183,9 +183,12 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setOperationAction(ISD::ConstantPool, MVT::i64, Custom); setOperationAction(ISD::JumpTable, MVT::i64, Custom); - // RET must be custom lowered, to meet ABI requirements + // RET must be custom lowered, to meet ABI requirements. setOperationAction(ISD::RET , MVT::Other, Custom); + // TRAP is legal. + setOperationAction(ISD::TRAP, MVT::Other, Legal); + // VASTART needs to be custom lowered to use the VarArgsFrameIndex setOperationAction(ISD::VASTART , MVT::Other, Custom); diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 0355d95..b08f186 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -298,6 +298,17 @@ class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, let Inst{31} = 0; } +class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { + let Pattern = pattern; + let Inst{6-10} = 31; + let Inst{11-15} = 0; + let Inst{16-20} = 0; + let Inst{21-30} = xo; + let Inst{31} = 0; +} + class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 3e0e605..b4b6080 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -575,6 +575,9 @@ def STWCX : XForm_1<31, 150, (outs), (ins GPRC:$rS, memrr:$dst), [(PPCstcx GPRC:$rS, xoaddr:$dst)]>, isDOT; +let isBarrier = 1, hasCtrlDep = 1 in +def TRAP : XForm_24<31, 4, (outs), (ins), "trap", LdStGeneral, [(trap)]>; + //===----------------------------------------------------------------------===// // PPC32 Load Instructions. // diff --git a/lib/Target/PowerPC/README.txt b/lib/Target/PowerPC/README.txt index 55baf8d..e5d4002 100644 --- a/lib/Target/PowerPC/README.txt +++ b/lib/Target/PowerPC/README.txt @@ -3,7 +3,6 @@ TODO: * gpr0 allocation * implement do-loop -> bdnz transform -* Implement __builtin_trap (ISD::TRAP) as 'tw 31, 0, 0' aka 'trap'. * lmw/stmw pass a la arm load store optimizer for prolog/epilog ===-------------------------------------------------------------------------=== |