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authorKevin Qin <Kevin.Qin@arm.com>2013-11-19 01:40:25 +0000
committerKevin Qin <Kevin.Qin@arm.com>2013-11-19 01:40:25 +0000
commit282a979dddff8d06a744c1b686fb3b7a7619d0f4 (patch)
tree120b5d03e6b35bade22ddc286bb16d78f4827b01 /lib/Target
parent01dd5728cc897777da95a7f4672b5a2540d52564 (diff)
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implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/AArch64/AArch64InstrNEON.td10
-rw-r--r--lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp2
2 files changed, 12 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td
index 50c3a56..6332745 100644
--- a/lib/Target/AArch64/AArch64InstrNEON.td
+++ b/lib/Target/AArch64/AArch64InstrNEON.td
@@ -3284,6 +3284,11 @@ multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
let isCommutable = Commutable in {
def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
opnode, VPR128, VPR64, v8i16, v8i8>;
+
+ def _1q1d : NeonI_3VDiff<0b0, u, 0b11, opcode,
+ (outs VPR128:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
+ asmop # "\t$Rd.1q, $Rn.1d, $Rm.1d",
+ [], NoItinerary>;
}
}
@@ -3295,6 +3300,11 @@ multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
!cast<PatFrag>(opnode # "_16B"),
v8i16, v16i8>;
+
+ def _1q2d : NeonI_3VDiff<0b1, u, 0b11, opcode,
+ (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
+ asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
+ [], NoItinerary>;
}
}
diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 34abe85..c351dbe 100644
--- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -1639,6 +1639,7 @@ AArch64AsmParser::IdentifyRegister(unsigned &RegNum, SMLoc &RegEndLoc,
// See if it's a 128-bit layout first.
Layout = StringSwitch<const char *>(LayoutText)
+ .Case(".q", ".q").Case(".1q", ".1q")
.Case(".d", ".d").Case(".2d", ".2d")
.Case(".s", ".s").Case(".4s", ".4s")
.Case(".h", ".h").Case(".8h", ".8h")
@@ -1737,6 +1738,7 @@ AArch64AsmParser::ParseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
case 'h': NumLanes = 8; break;
case 's': NumLanes = 4; break;
case 'd': NumLanes = 2; break;
+ case 'q': NumLanes = 1; break;
}
}