diff options
author | Hal Finkel <hfinkel@anl.gov> | 2013-06-28 20:00:07 +0000 |
---|---|---|
committer | Hal Finkel <hfinkel@anl.gov> | 2013-06-28 20:00:07 +0000 |
commit | 2c77a625b79908f6e1238890caae630d28c48bee (patch) | |
tree | 16e3da165c33a00d5de0e7d73f0e35b2b2dafb99 /lib/Target | |
parent | 3ca4fa7c265b9f42d2c6bad2362c6ba6640d1b92 (diff) | |
download | external_llvm-2c77a625b79908f6e1238890caae630d28c48bee.zip external_llvm-2c77a625b79908f6e1238890caae630d28c48bee.tar.gz external_llvm-2c77a625b79908f6e1238890caae630d28c48bee.tar.bz2 |
Fix a PPC rlwimi instruction-selection bug
Under certain (evidently rare) circumstances, this code used to convert OR(a,
AND(x, y)) into OR(a, x). This was incorrect.
While there, I've added a comment to the code immediately above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185201 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 35f4b7c..f8d990c 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -447,10 +447,10 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { unsigned SHOpc = Op1.getOperand(0).getOpcode(); if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) { + // Note that Value must be in range here (less than 32) because + // otherwise there would not be any bits set in InsertMask. Op1 = Op1.getOperand(0).getOperand(0); SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; - } else { - Op1 = Op1.getOperand(0); } } |