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| author | Nate Begeman <natebegeman@mac.com> | 2004-10-16 20:43:38 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2004-10-16 20:43:38 +0000 |
| commit | 2d4c98d79b5526aaf94b87d21a7d672f35b183a9 (patch) | |
| tree | db400110a282a910374e0118b74cdd6ebcfb3232 /lib/Target | |
| parent | 6e758aee74a500c62796313689530241a4957cf9 (diff) | |
| download | external_llvm-2d4c98d79b5526aaf94b87d21a7d672f35b183a9.zip external_llvm-2d4c98d79b5526aaf94b87d21a7d672f35b183a9.tar.gz external_llvm-2d4c98d79b5526aaf94b87d21a7d672f35b183a9.tar.bz2 | |
Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly
flag rotate left word immediate then mask insert (rlwimi) as a two-address
instruction, and update the ISel usage of the instruction accordingly.
This will allow us to properly schedule rlwimi, and use it to efficiently
codegen bitfield operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17068 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/PowerPC/PPC32ISelSimple.cpp | 18 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 6 |
2 files changed, 12 insertions, 12 deletions
diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp index 247da62..6ee47e0 100644 --- a/lib/Target/PowerPC/PPC32ISelSimple.cpp +++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp @@ -2550,25 +2550,23 @@ void PPC32ISel::emitShiftOperation(MachineBasicBlock *MBB, // Longs, as usual, are handled specially... if (Class == cLong) { // If we have a constant shift, we can generate much more efficient code - // than otherwise... - // + // than for a variable shift by using the rlwimi instruction. if (ConstantUInt *CUI = dyn_cast<ConstantUInt>(ShiftAmount)) { unsigned Amount = CUI->getValue(); if (Amount < 32) { + unsigned TempReg = makeAnotherReg(ResultTy); if (isLeftShift) { - // FIXME: RLWIMI is a use-and-def of DestReg+1, but that violates SSA - BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg) + BuildMI(*MBB, IP, PPC::RLWINM, 4, TempReg).addReg(SrcReg) .addImm(Amount).addImm(0).addImm(31-Amount); - BuildMI(*MBB, IP, PPC::RLWIMI, 5).addReg(DestReg).addReg(SrcReg+1) - .addImm(Amount).addImm(32-Amount).addImm(31); + BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg).addReg(TempReg) + .addReg(SrcReg+1).addImm(Amount).addImm(32-Amount).addImm(31); BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1) .addImm(Amount).addImm(0).addImm(31-Amount); } else { - // FIXME: RLWIMI is a use-and-def of DestReg, but that violates SSA - BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg+1).addReg(SrcReg+1) + BuildMI(*MBB, IP, PPC::RLWINM, 4, TempReg).addReg(SrcReg+1) .addImm(32-Amount).addImm(Amount).addImm(31); - BuildMI(*MBB, IP, PPC::RLWIMI, 5).addReg(DestReg+1).addReg(SrcReg) - .addImm(32-Amount).addImm(0).addImm(Amount-1); + BuildMI(*MBB, IP, PPC::RLWIMI, 5, DestReg+1).addReg(TempReg) + .addReg(SrcReg).addImm(32-Amount).addImm(0).addImm(Amount-1); BuildMI(*MBB, IP, PPC::RLWINM, 4, DestReg).addReg(SrcReg) .addImm(32-Amount).addImm(Amount).addImm(31); } diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index d09636a..7009af2 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -412,9 +412,11 @@ def FSUBS : AForm_2<59, 20, 0, 0, 0, // M-Form instructions. rotate and mask instructions. // +let isTwoAddress = 1 in { def RLWIMI : MForm_2<20, 0, 0, 0, - (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), - "rlwimi $rA, $rS, $SH, $MB, $ME">; + (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, + u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">; +} def RLWINM : MForm_2<21, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), "rlwinm $rA, $rS, $SH, $MB, $ME">; |