rename isStore -> mayStore to more accurately reflect what it captures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8

10 files changed, 13 insertions, 13 deletions

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 04b497e..da294fe 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -892,7 +892,7 @@ def STRB : AI2<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
                [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
 
 // Store doubleword
-let isStore = 1 in
+let mayStore = 1 in
 def STRD : AI3<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StFrm,
                "str", "d $src, $addr",
                []>, Requires<[IsARM, HasV5T]>;
@@ -945,7 +945,7 @@ def LDM : AXI4<0x0, (outs),
                LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
                []>;
 
-let isStore = 1 in
+let mayStore = 1 in
 def STM : AXI4<0x0, (outs),
                (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
                StFrm, "stm${p}${addr:submode} $addr, $src1",
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index 4611a3e..2782f7d 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -294,7 +294,7 @@ def tSTRspi : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
                    "str $src, $addr",
                    [(store GPR:$src, t_addrmode_sp:$addr)]>;
 
-let isStore = 1 in {
+let mayStore = 1 in {
 // Special instruction for spill. It cannot clobber condition register
 // when it's expanded by eliminateCallFramePseudoInstr().
 def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
@@ -311,7 +311,7 @@ let isLoad = 1 in
 def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
                "pop $dst1", []>;
 
-let isStore = 1 in
+let mayStore = 1 in
 def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
                 "push $src1", []>;
 
diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td
index d0ae52f..89523f7 100644
--- a/lib/Target/ARM/ARMInstrVFP.td
+++ b/lib/Target/ARM/ARMInstrVFP.td
@@ -122,7 +122,7 @@ def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
                   []>;
 } // isLoad
 
-let isStore = 1 in {
+let mayStore = 1 in {
 def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
                            variable_ops),
                  "fstm${addr:submode}d${p} ${addr:base}, $src1",
@@ -132,7 +132,7 @@ def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
                            variable_ops),
                  "fstm${addr:submode}s${p} ${addr:base}, $src1",
                  []>;
-} // isStore
+} // mayStore
 
 // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
 
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index b940052..ea775f7 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -905,7 +905,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
         MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
       else  // tLDR has an extra register operand.
         MI.addOperand(MachineOperand::CreateReg(0, false));
-    } else if (TII.isStore(Opcode)) {
+    } else if (TII.mayStore(Opcode)) {
       // FIXME! This is horrific!!! We need register scavenging.
       // Our temporary workaround has marked r3 unavailable. Of course, r3 is
       // also a ABI register so it's possible that is is the register that is
diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td
index 5276c42..f308228 100644
--- a/lib/Target/IA64/IA64InstrInfo.td
+++ b/lib/Target/IA64/IA64InstrInfo.td
@@ -541,7 +541,7 @@ def CADDIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s22imm:$imm, PR
 def SUBIMM8 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s8imm:$imm, GR:$src2),
   "sub $dst = $imm, $src2">, isA;
 
-let isStore = 1 in {
+let mayStore = 1 in {
   def ST1 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
     "st1 [$dstPtr] = $value">, isM;
   def ST2 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index c11e0dd..03570aa 100644
--- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -73,7 +73,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
   const TargetInstrDescriptor &TID = TII.get(Opcode);
   
   isLoad  = TID.Flags & M_LOAD_FLAG;
-  isStore = TID.Flags & M_STORE_FLAG;
+  isStore = TID.Flags & M_MAY_STORE_FLAG;
   
   unsigned TSFlags = TID.TSFlags;
   
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td
index 80d7fba..8016783 100644
--- a/lib/Target/PowerPC/PPCInstr64Bit.td
+++ b/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -513,7 +513,7 @@ def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
                     RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
                     isPPC64;
 
-let isStore = 1 in
+let mayStore = 1 in
 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
                    "stdux $rS, $dst", LdStSTD,
                    []>, isPPC64;
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 82818d6..dc1ba09 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -638,7 +638,7 @@ def STWX  : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
                    [(store GPRC:$rS, xaddr:$dst)]>,
                    PPC970_DGroup_Cracked;
                    
-let isStore = 1 in {
+let mayStore = 1 in {
 def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
                    "stwux $rS, $rA, $rB", LdStGeneral,
                    []>;
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 5747ac3..2e12070 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -191,7 +191,7 @@ class Instruction {
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
   bit isLoad       = 0;     // Is this instruction a load instruction?
-  bit isStore      = 0;     // Is this instruction a store instruction?
+  bit mayStore     = 0;     // Can this instruction modify memory?
   bit isImplicitDef = 0;    // Is this instruction an implicit def instruction?
   bit isTwoAddress = 0;     // Is this a two address instruction?
   bit isConvertibleToThreeAddress = 0;  // Can this 2-addr instruction promote?
diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index 4659ebd..6a7da0c 100644
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -189,7 +189,7 @@ def SDNPHasChain    : SDNodeProperty;   // R/W chain operand and result
 def SDNPOutFlag     : SDNodeProperty;   // Write a flag result
 def SDNPInFlag      : SDNodeProperty;   // Read a flag operand
 def SDNPOptInFlag   : SDNodeProperty;   // Optionally read a flag operand
-def SDNPMayStore    : SDNodeProperty;   // May write to memory, sets 'isStore'.
+def SDNPMayStore    : SDNodeProperty;   // May write to memory, sets 'mayStore'.
 
 //===----------------------------------------------------------------------===//
 // Selection DAG Node definitions.