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authorJim Grosbach <grosbach@apple.com>2011-07-29 20:02:39 +0000
committerJim Grosbach <grosbach@apple.com>2011-07-29 20:02:39 +0000
commit33768dba54ebd6ba4315345316cf426af7a78639 (patch)
tree4eddb5863641ba5f67e7c783135c9567fd57b669 /lib/Target
parent6e8bb8a0cb08a26e92fd1c60a64f357a41698bae (diff)
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ARM CPS mode immediate is 5 bits, not 4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136505 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index b7c245f..cf4ef65 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1319,13 +1319,13 @@ class CPS<dag iops, string asm_ops>
}
let M = 1 in
- def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_15:$mode),
+ def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
"$imod\t$iflags, $mode">;
let mode = 0, M = 0 in
def CPS2p : CPS<(ins imod_op:$imod, iflags_op:$iflags), "$imod\t$iflags">;
let imod = 0, iflags = 0, M = 1 in
- def CPS1p : CPS<(ins imm0_15:$mode), "\t$mode">;
+ def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
// Preload signals the memory system of possible future data/instruction access.
// These are for disassembly only.