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| author | Vincent Lejeune <vljn@ovi.com> | 2013-11-16 16:24:41 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-11-16 16:24:41 +0000 |
| commit | 411079785388290738049dd099bff8755e6a2c8d (patch) | |
| tree | e79a958d491354edc7924d409e6b31962f9f063a /lib/Target | |
| parent | 0fb32eb56aabb24950bbfecc927596a3fffabcb1 (diff) | |
| download | external_llvm-411079785388290738049dd099bff8755e6a2c8d.zip external_llvm-411079785388290738049dd099bff8755e6a2c8d.tar.gz external_llvm-411079785388290738049dd099bff8755e6a2c8d.tar.bz2 | |
R600: Make dot_4 instructions predicable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194927 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/R600/R600InstrInfo.cpp | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/lib/Target/R600/R600InstrInfo.cpp b/lib/Target/R600/R600InstrInfo.cpp index 8436d5f..1f47416 100644 --- a/lib/Target/R600/R600InstrInfo.cpp +++ b/lib/Target/R600/R600InstrInfo.cpp @@ -1009,6 +1009,20 @@ R600InstrInfo::PredicateInstruction(MachineInstr *MI, return true; } + if (MI->getOpcode() == AMDGPU::DOT_4) { + MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_X)) + .setReg(Pred[2].getReg()); + MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Y)) + .setReg(Pred[2].getReg()); + MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_Z)) + .setReg(Pred[2].getReg()); + MI->getOperand(getOperandIdx(*MI, AMDGPU::OpName::pred_sel_W)) + .setReg(Pred[2].getReg()); + MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); + MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); + return true; + } + if (PIdx != -1) { MachineOperand &PMO = MI->getOperand(PIdx); PMO.setReg(Pred[2].getReg()); @@ -1217,6 +1231,11 @@ MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction( AMDGPU::OpName::src1_sel, }; + MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(), + getSlotedOps(AMDGPU::OpName::pred_sel, Slot))); + MIB->getOperand(getOperandIdx(Opcode, AMDGPU::OpName::pred_sel)) + .setReg(MO.getReg()); + for (unsigned i = 0; i < 14; i++) { MachineOperand &MO = MI->getOperand( getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot))); |