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| author | Jim Grosbach <grosbach@apple.com> | 2011-08-19 18:49:59 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-08-19 18:49:59 +0000 |
| commit | 48ff5ffe9e2a90f853ce3645b1b97ea7885eccf1 (patch) | |
| tree | 79cabd12b5ffbe98611c39e6044a69a775bed350 /lib/Target | |
| parent | 09f6e0dfda121251c5da7dba04b8b72d5572b0df (diff) | |
| download | external_llvm-48ff5ffe9e2a90f853ce3645b1b97ea7885eccf1.zip external_llvm-48ff5ffe9e2a90f853ce3645b1b97ea7885eccf1.tar.gz external_llvm-48ff5ffe9e2a90f853ce3645b1b97ea7885eccf1.tar.bz2 | |
Thumb assembly parsing and encoding for LDRB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb.td | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 16 |
2 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 0c7e349..35a745a 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -179,11 +179,13 @@ def t_addrmode_is2 : Operand<i32>, // t_addrmode_is1 := reg + imm5 // +def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } def t_addrmode_is1 : Operand<i32>, ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { let EncoderMethod = "getAddrModeISOpValue"; let DecoderMethod = "DecodeThumbAddrModeIS"; let PrintMethod = "printThumbAddrModeImm5S1Operand"; + let ParserMatchClass = t_addrmode_is1_asm_operand; let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); } diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index b6fce29..d04b9b7 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -628,6 +628,15 @@ public: int64_t Val = Mem.OffsetImm->getValue(); return Val >= 0 && Val <= 124 && (Val % 4) == 0; } + bool isMemThumbRIs1() const { + if (Kind != Memory || Mem.OffsetRegNum != 0 || + !isARMLowRegister(Mem.BaseRegNum)) + return false; + // Immediate offset in range [0, 31]. + if (!Mem.OffsetImm) return true; + int64_t Val = Mem.OffsetImm->getValue(); + return Val >= 0 && Val <= 31; + } bool isMemThumbSPI() const { if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP) return false; @@ -1000,6 +1009,13 @@ public: Inst.addOperand(MCOperand::CreateImm(Val)); } + void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { + assert(N == 2 && "Invalid number of operands!"); + int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0; + Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); + Inst.addOperand(MCOperand::CreateImm(Val)); + } + void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0; |
