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author | Bill Wendling <isanbard@gmail.com> | 2009-05-30 01:09:53 +0000 |
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committer | Bill Wendling <isanbard@gmail.com> | 2009-05-30 01:09:53 +0000 |
commit | 51b16f473759c1546acbf308a5d3f3e7bf3ea23c (patch) | |
tree | 1c33a0bd47e7b0fc26b2c57cb67cbb6b62e23ef4 /lib/Target | |
parent | 4d4eab219a96203f58452b39b4e94e234dfe4007 (diff) | |
download | external_llvm-51b16f473759c1546acbf308a5d3f3e7bf3ea23c.zip external_llvm-51b16f473759c1546acbf308a5d3f3e7bf3ea23c.tar.gz external_llvm-51b16f473759c1546acbf308a5d3f3e7bf3ea23c.tar.bz2 |
Untabification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72604 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 2 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPUISelDAGToDAG.cpp | 4 | ||||
-rw-r--r-- | lib/Target/PIC16/PIC16ISelLowering.cpp | 2 | ||||
-rw-r--r-- | lib/Target/PIC16/PIC16ISelLowering.h | 2 | ||||
-rw-r--r-- | lib/Target/TargetRegisterInfo.cpp | 4 | ||||
-rw-r--r-- | lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp | 4 | ||||
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 12 | ||||
-rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.cpp | 4 | ||||
-rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.h | 2 | ||||
-rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 10 |
10 files changed, 23 insertions, 23 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index 964f50a..199858f 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -1522,7 +1522,7 @@ unsigned ARMRegisterInfo::getEHHandlerRegister() const { } int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); + return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } #include "ARMGenRegisterInfo.inc" diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index dd2ef64..779d75d 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -872,12 +872,12 @@ SPUDAGToDAGISel::Select(SDValue Op) { } else if (OpVT == MVT::v2f64) { Opc = SPU::XORfnegvec; signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl, - MVT::v2i64, + MVT::v2i64, negConst, negConst)); } return CurDAG->getTargetNode(Opc, dl, OpVT, - Op.getOperand(0), SDValue(signMask, 0)); + Op.getOperand(0), SDValue(signMask, 0)); } else if (Opc == ISD::FABS) { if (OpVT == MVT::f64) { SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl); diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index f061507..c16b4ad 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -535,7 +535,7 @@ void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG, // Extract the lo component. Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op, DAG.getConstant(0, MVT::i8)); - + // extract the hi component Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op, DAG.getConstant(1, MVT::i8)); diff --git a/lib/Target/PIC16/PIC16ISelLowering.h b/lib/Target/PIC16/PIC16ISelLowering.h index 483bb3f..ca9650d 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.h +++ b/lib/Target/PIC16/PIC16ISelLowering.h @@ -49,7 +49,7 @@ namespace llvm { RRF, // Rotate right through carry CALL, // PIC16 Call instruction CALLW, // PIC16 CALLW instruction - SUBCC, // Compare for equality or inequality. + SUBCC, // Compare for equality or inequality. SELECT_ICC, // Psuedo to be caught in schedular and expanded to brcond. BRCOND, // Conditional branch. Dummy diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp index d075c57..a84fdaa 100644 --- a/lib/Target/TargetRegisterInfo.cpp +++ b/lib/Target/TargetRegisterInfo.cpp @@ -23,9 +23,9 @@ using namespace llvm; TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, regclass_iterator RCB, regclass_iterator RCE, int CFSO, int CFDO, - const unsigned* subregs, const unsigned subregsize, + const unsigned* subregs, const unsigned subregsize, const unsigned* superregs, const unsigned superregsize, - const unsigned* aliases, const unsigned aliasessize) + const unsigned* aliases, const unsigned aliasessize) : SubregHash(subregs), SubregHashSize(subregsize), SuperregHash(superregs), SuperregHashSize(superregsize), AliasesHash(aliases), AliasesHashSize(aliasessize), diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp index 4c7ccbd..8afe2ea 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp @@ -451,7 +451,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, break; case TLSModel::LocalDynamic: // O << "@TLSLD"; // local dynamic not implemented - O << "@TLSGD"; + O << "@TLSGD"; break; case TLSModel::InitialExec: if (Subtarget->is64Bit()) { @@ -465,7 +465,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, if (Subtarget->is64Bit()) O << "@TPOFF"; else - O << "@NTPOFF"; + O << "@NTPOFF"; break; default: assert (0 && "Unknown TLS model"); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 0136f90..882ee3a 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -6974,7 +6974,7 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, // Insert instructions into newMBB based on incoming instruction assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 && - "unexpected number of operands"); + "unexpected number of operands"); DebugLoc dl = bInstr->getDebugLoc(); MachineOperand& destOper = bInstr->getOperand(0); MachineOperand* argOpers[2 + X86AddrNumOperands]; @@ -7084,7 +7084,7 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, // Insert instructions into newMBB based on incoming instruction // There are 8 "real" operands plus 9 implicit def/uses, ignored here. assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 && - "unexpected number of operands"); + "unexpected number of operands"); MachineOperand& dest1Oper = bInstr->getOperand(0); MachineOperand& dest2Oper = bInstr->getOperand(1); MachineOperand* argOpers[2 + X86AddrNumOperands]; @@ -7131,7 +7131,7 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, int valArgIndx = lastAddrIndx + 1; assert((argOpers[valArgIndx]->isReg() || - argOpers[valArgIndx]->isImm()) && + argOpers[valArgIndx]->isImm()) && "invalid operand"); unsigned t5 = F->getRegInfo().createVirtualRegister(RC); unsigned t6 = F->getRegInfo().createVirtualRegister(RC); @@ -7143,9 +7143,9 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, MIB.addReg(tt1); (*MIB).addOperand(*argOpers[valArgIndx]); assert(argOpers[valArgIndx + 1]->isReg() == - argOpers[valArgIndx]->isReg()); + argOpers[valArgIndx]->isReg()); assert(argOpers[valArgIndx + 1]->isImm() == - argOpers[valArgIndx]->isImm()); + argOpers[valArgIndx]->isImm()); if (argOpers[valArgIndx + 1]->isReg()) MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); else @@ -7226,7 +7226,7 @@ X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, DebugLoc dl = mInstr->getDebugLoc(); // Insert instructions into newMBB based on incoming instruction assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 && - "unexpected number of operands"); + "unexpected number of operands"); MachineOperand& destOper = mInstr->getOperand(0); MachineOperand* argOpers[2 + X86AddrNumOperands]; int numArgs = mInstr->getNumOperands() - 1; diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index 0402f59..504d202 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -431,8 +431,8 @@ void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, } bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector<CalleeSavedInfo> &CSI) const + MachineBasicBlock::iterator MI, + const std::vector<CalleeSavedInfo> &CSI) const { if (CSI.empty()) { return true; diff --git a/lib/Target/XCore/XCoreInstrInfo.h b/lib/Target/XCore/XCoreInstrInfo.h index 965ad36..0870886 100644 --- a/lib/Target/XCore/XCoreInstrInfo.h +++ b/lib/Target/XCore/XCoreInstrInfo.h @@ -90,7 +90,7 @@ public: SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const; - + virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI) const; diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 5faae71..65cd4fe 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -50,17 +50,17 @@ def SDT_XCoreAddress : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress, - []>; + []>; def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress, - []>; + []>; def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress, - []>; + []>; def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>; -def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, - [SDNPHasChain]>; +def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp, + [SDNPHasChain]>; // These are target-independent nodes, but have target-specific formats. def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; |