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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2008-07-30 19:00:31 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2008-07-30 19:00:31 +0000 |
| commit | 7030ae7728fb7d5f937f72943d73fc69c4d451c0 (patch) | |
| tree | 580083e7963b675a2277d66c2d79f9835d074c17 /lib/Target | |
| parent | 0b12aef49087b57d276ed760a83525d1e2602144 (diff) | |
| download | external_llvm-7030ae7728fb7d5f937f72943d73fc69c4d451c0.zip external_llvm-7030ae7728fb7d5f937f72943d73fc69c4d451c0.tar.gz external_llvm-7030ae7728fb7d5f937f72943d73fc69c4d451c0.tar.bz2 | |
Added pattern for floating point zero immediate (avoiding a constant pool
access).
Added pattern to match bitconvert node.
Fixed MTC1 asm string bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54229 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrFPU.td | 16 |
2 files changed, 16 insertions, 3 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 29dc7a3..4bceb20 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -77,6 +77,9 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM) } else addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); + // Legal fp constants + addLegalFPImmediate(APFloat(+0.0f)); + // Load extented operations for i1 types must be promoted setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote); setLoadXAction(ISD::ZEXTLOAD, MVT::i1, Promote); diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index b459815..312cc0b 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -194,13 +194,13 @@ let fd = 0 in { "mfc1 $rt, $fs", []>; def MTC1 : FFR<0x11, 0x00, 0x04, (outs FGR32:$fs), (ins CPURegs:$rt), - "mtc1 $fs, $rt", []>; + "mtc1 $rt, $fs", []>; def MFC1A : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins AFGR32:$fs), "mfc1 $rt, $fs", []>; def MTC1A : FFR<0x11, 0x00, 0x04, (outs AFGR32:$fs), (ins CPURegs:$rt), - "mtc1 $fs, $rt", []>; + "mtc1 $rt, $fs", []>; } /// Floating Point Memory Instructions @@ -324,8 +324,18 @@ def Select_FCC_D32 : PseudoFPSelCC<AFGR64, "# MipsSelect_FCC_D32_f32">, //===----------------------------------------------------------------------===// // Floating Point Patterns //===----------------------------------------------------------------------===// +def fpimm0 : PatLeaf<(fpimm), [{ + return N->isExactlyValue(+0.0); +}]>; + +def : Pat<(f32 fpimm0), (MTC1 ZERO)>, Requires<[IsSingleFloat]>; +def : Pat<(f32 fpimm0), (MTC1A ZERO)>, Requires<[In32BitMode]>; + def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVTS_W32 (MTC1 CPURegs:$src))>; def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVTD_W32 (MTC1 CPURegs:$src))>; + def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_SO32 FGR32:$src))>; -def : Pat<(i32 (fp_to_sint AFGR32:$src)), (MFC1 (TRUNC_W_AS32 AFGR32:$src))>; +def : Pat<(i32 (fp_to_sint AFGR32:$src)), (MFC1A (TRUNC_W_AS32 AFGR32:$src))>; +def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>; +def : Pat<(i32 (bitconvert AFGR32:$src)), (MFC1A AFGR32:$src)>; |