Added a way for TargetLowering to specify what values can be used as the

scale component of the target addressing mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26802 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 14 insertions, 4 deletions

diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 041eddf..8985a43 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -84,7 +84,7 @@ bool PPCTargetMachine::addPassesToEmitFile(PassManager &PM,
   if (FileType != TargetMachine::AssemblyFile) return true;
   
   // Run loop strength reduction before anything else.
-  if (!Fast) PM.add(createLoopStrengthReducePass(1, &TLInfo));
+  if (!Fast) PM.add(createLoopStrengthReducePass(&TLInfo));
 
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
@@ -138,7 +138,7 @@ void PPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
   TM.setRelocationModel(Reloc::DynamicNoPIC);
 
   // Run loop strength reduction before anything else.
-  PM.add(createLoopStrengthReducePass(1, TM.getTargetLowering()));
+  PM.add(createLoopStrengthReducePass(TM.getTargetLowering()));
 
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index bf0d6d8..148c7f8 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -49,6 +49,16 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
   setSchedulingPreference(SchedulingForRegPressure);
   setShiftAmountFlavor(Mask);   // shl X, 32 == shl X, 0
   setStackPointerRegisterToSaveRestore(X86::ESP);
+
+  // Add legal addressing mode scale values.
+  addLegalAddressScale(8);
+  addLegalAddressScale(4);
+  addLegalAddressScale(2);
+  // Enter the ones which require both scale + index last. These are more
+  // expensive.
+  addLegalAddressScale(9);
+  addLegalAddressScale(5);
+  addLegalAddressScale(3);
   
   // Set up the register classes.
   addRegisterClass(MVT::i8, X86::R8RegisterClass);
diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 2de8cc0..3d5a6f8 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -97,7 +97,7 @@ bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
       FileType != TargetMachine::ObjectFile) return true;
 
   // Run loop strength reduction before anything else.
-  if (EnableX86LSR) PM.add(createLoopStrengthReducePass(1, &TLInfo));
+  if (EnableX86LSR) PM.add(createLoopStrengthReducePass(&TLInfo));
 
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());
@@ -166,7 +166,7 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
 
   // Run loop strength reduction before anything else.
   if (EnableX86LSR)
-    PM.add(createLoopStrengthReducePass(1, TM.getTargetLowering()));
+    PM.add(createLoopStrengthReducePass(TM.getTargetLowering()));
 
   // FIXME: Implement efficient support for garbage collection intrinsics.
   PM.add(createLowerGCPass());