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| author | Evan Cheng <evan.cheng@apple.com> | 2011-06-21 19:00:54 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-06-21 19:00:54 +0000 |
| commit | 734f63bed974a0196e85b0f82c1b6b4e5b891192 (patch) | |
| tree | a99cae44992301d06c1cead4bb18472a52dcd7b7 /lib/Target | |
| parent | 38c892624bc66cad98a81e080d235f4e33122562 (diff) | |
| download | external_llvm-734f63bed974a0196e85b0f82c1b6b4e5b891192.zip external_llvm-734f63bed974a0196e85b0f82c1b6b4e5b891192.tar.gz external_llvm-734f63bed974a0196e85b0f82c1b6b4e5b891192.tar.bz2 | |
Reorg. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133533 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 49 |
1 files changed, 26 insertions, 23 deletions
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 60fff05..090670b 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1206,29 +1206,6 @@ def t2SUBrSPs : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$imm), } } // end isCodeGenOnly = 1 -// Signed and unsigned division on v7-M -def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi, - "sdiv", "\t$Rd, $Rn, $Rm", - [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>, - Requires<[HasDivide, IsThumb2]> { - let Inst{31-27} = 0b11111; - let Inst{26-21} = 0b011100; - let Inst{20} = 0b1; - let Inst{15-12} = 0b1111; - let Inst{7-4} = 0b1111; -} - -def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi, - "udiv", "\t$Rd, $Rn, $Rm", - [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>, - Requires<[HasDivide, IsThumb2]> { - let Inst{31-27} = 0b11111; - let Inst{26-21} = 0b011101; - let Inst{20} = 0b1; - let Inst{15-12} = 0b1111; - let Inst{7-4} = 0b1111; -} - //===----------------------------------------------------------------------===// // Load / store Instructions. // @@ -2560,6 +2537,32 @@ def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd), "\t$Ra, $Rd, $Rm, $Rn", []>; //===----------------------------------------------------------------------===// +// Division Instructions. +// Signed and unsigned division on v7-M +// +def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi, + "sdiv", "\t$Rd, $Rn, $Rm", + [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>, + Requires<[HasDivide, IsThumb2]> { + let Inst{31-27} = 0b11111; + let Inst{26-21} = 0b011100; + let Inst{20} = 0b1; + let Inst{15-12} = 0b1111; + let Inst{7-4} = 0b1111; +} + +def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi, + "udiv", "\t$Rd, $Rn, $Rm", + [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>, + Requires<[HasDivide, IsThumb2]> { + let Inst{31-27} = 0b11111; + let Inst{26-21} = 0b011101; + let Inst{20} = 0b1; + let Inst{15-12} = 0b1111; + let Inst{7-4} = 0b1111; +} + +//===----------------------------------------------------------------------===// // Misc. Arithmetic Instructions. // |