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| author | Jim Grosbach <grosbach@apple.com> | 2012-01-25 19:52:01 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2012-01-25 19:52:01 +0000 |
| commit | 74423e32ce7f426b624bfb0c31481bcf6a36394d (patch) | |
| tree | 1ae2c4dda338f41bdf18c850a1f80f8d4f93ff8e /lib/Target | |
| parent | 0c8515f0969e0a4d0b5313c6ceadd5ff4dab5998 (diff) | |
| download | external_llvm-74423e32ce7f426b624bfb0c31481bcf6a36394d.zip external_llvm-74423e32ce7f426b624bfb0c31481bcf6a36394d.tar.gz external_llvm-74423e32ce7f426b624bfb0c31481bcf6a36394d.tar.bz2 | |
ARM assemly parsing and validation of IT instruction.
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 13 |
2 files changed, 14 insertions, 3 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index e319047..ce3e770 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -5179,3 +5179,7 @@ def : ARMInstAlias<"mul${s}${p} $Rn, $Rm", // "neg" is and alias for "rsb rd, rn, #0" def : ARMInstAlias<"neg${s}${p} $Rd, $Rm", (RSBri GPR:$Rd, GPR:$Rm, 0, pred:$p, cc_out:$s)>; + +// 'it' blocks in ARM mode just validate the predicates. The IT itself +// is discarded. +def ITasm : ARMAsmPseudo<"it$mask $cc", (ins it_pred:$cc, it_mask:$mask)>; diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 94604c9..ec9baf9 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -5080,10 +5080,11 @@ validateInstruction(MCInst &Inst, const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); SMLoc Loc = Operands[0]->getStartLoc(); // Check the IT block state first. - // NOTE: In Thumb mode, the BKPT instruction has the interesting property of - // being allowed in IT blocks, but not being predicable. It just always + // NOTE: BKPT instruction has the interesting property of being + // allowed in IT blocks, but not being predicable. It just always // executes. - if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) { + if (inITBlock() && Inst.getOpcode() != ARM::tBKPT && + Inst.getOpcode() != ARM::BKPT) { unsigned bit = 1; if (ITState.FirstCond) ITState.FirstCond = false; @@ -7048,6 +7049,7 @@ processInstruction(MCInst &Inst, } return false; } + case ARM::ITasm: case ARM::t2IT: { // The mask bits for all but the first condition are represented as // the low bit of the condition code value implies 't'. We currently @@ -7154,6 +7156,11 @@ MatchAndEmitInstruction(SMLoc IDLoc, // block. forwardITPosition(); + // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and + // doesn't actually encode. + if (Inst.getOpcode() == ARM::ITasm) + return false; + Out.EmitInstruction(Inst); return false; case Match_MissingFeature: |