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authorBill Wendling <isanbard@gmail.com>2010-08-10 21:38:11 +0000
committerBill Wendling <isanbard@gmail.com>2010-08-10 21:38:11 +0000
commit75486dbf4e9611f2070bf13b874f78a5587ed7ff (patch)
tree28a6fa52f0bf2d7cb8c427b72c47362a3421374f /lib/Target
parenta516e94cf159b9ea02af31872fc59b7ceeef7965 (diff)
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Turn optimize compares back on with fix. We needed to test that a machine op was
a register before checking if it was defined. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110733 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/ARM/ARMBaseInstrInfo.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 7e1c84e..5881a12 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1386,7 +1386,7 @@ ConvertToSetZeroFlag(MachineInstr *MI, MachineInstr *CmpInstr) const {
for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
const MachineOperand &MO = Instr.getOperand(IO);
- if (!MO.isDef() || !MO.isReg()) continue;
+ if (!MO.isReg() || !MO.isDef()) continue;
// This instruction modifies CPSR before the one we want to change. We
// can't do this transformation.