Add a note about a potential optimization for clz/ctz patterns for ARM

(and other targets).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149182 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 16 insertions, 0 deletions

diff --git a/lib/Target/ARM/README.txt b/lib/Target/ARM/README.txt
index 2f6842e..4fcaecf 100644
--- a/lib/Target/ARM/README.txt
+++ b/lib/Target/ARM/README.txt
@@ -699,3 +699,19 @@ test is equality test so it's more a conditional move rather than a select:
 
 Currently this is a ARM specific dag combine. We probably should make it into a
 target-neutral one.
+
+//===---------------------------------------------------------------------===//
+
+Optimize unnecessary checks for zero with __builtin_clz/ctz.  Those builtins
+are specified to be undefined at zero, so portable code must check for zero
+and handle it as a special case.  That is unnecessary on ARM where those
+operations are implemented in a way that is well-defined for zero.  For
+example:
+
+int f(int x) { return x ? __builtin_clz(x) : sizeof(int)*8; }
+
+should just be implemented with a CLZ instruction.  Since there are other
+targets, e.g., PPC, that share this behavior, it would be best to implement
+this in a target-independent way: we should probably fold that (when using
+"undefined at zero" semantics) to set the "defined at zero" bit and have
+the code generator expand out the right code.