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| author | Joel Jones <joel_k_jones@apple.com> | 2012-07-18 00:02:16 +0000 |
|---|---|---|
| committer | Joel Jones <joel_k_jones@apple.com> | 2012-07-18 00:02:16 +0000 |
| commit | 7c82e6a32a84e238c9e4e57dd43eaba540a79ce1 (patch) | |
| tree | ee690b3fa0c29940515aa6a66214f8190b7fc180 /lib/Target | |
| parent | 0b5f1aca32076e9a29dc3d716945d1ec6003c96e (diff) | |
| download | external_llvm-7c82e6a32a84e238c9e4e57dd43eaba540a79ce1.zip external_llvm-7c82e6a32a84e238c9e4e57dd43eaba540a79ce1.tar.gz external_llvm-7c82e6a32a84e238c9e4e57dd43eaba540a79ce1.tar.bz2 | |
More replacing of target-dependent intrinsics with target-indepdent
intrinsics. The second instruction(s) to be handled are the vector versions
of count set bits (ctpop).
The changes here are to clang so that it generates a target independent
vector ctpop when it sees an ARM dependent vector bits set count. The changes
in llvm are to match the target independent vector ctpop and in
VMCore/AutoUpgrade.cpp to update any existing bc files containing ARM
dependent vector pop counts with target-independent ctpops. There are also
changes to an existing test case in llvm for ARM vector count instructions and
to a test for the bitcode upgrade.
<rdar://problem/11892519>
There is deliberately no test for the change to clang, as so far as I know, no
consensus has been reached regarding how to test neon instructions in clang;
q.v. <rdar://problem/8762292>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160410 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMInstrNEON.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index c540d0d..d4afa33 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -4829,10 +4829,10 @@ defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, // VCNT : Vector Count One Bits def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, IIC_VCNTiD, "vcnt", "8", - v8i8, v8i8, int_arm_neon_vcnt>; + v8i8, v8i8, ctpop>; def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, IIC_VCNTiQ, "vcnt", "8", - v16i8, v16i8, int_arm_neon_vcnt>; + v16i8, v16i8, ctpop>; // Vector Swap def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0, |