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| author | Bob Wilson <bob.wilson@apple.com> | 2010-07-08 17:44:00 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-07-08 17:44:00 +0000 |
| commit | 8190173350f4e4d916d2307278955b133fba8a00 (patch) | |
| tree | b3933ae86aa243c234671a6de3d9b53efb9d4708 /lib/Target | |
| parent | b113cf2fedaf290242939c8f8c6f7e1438d46024 (diff) | |
| download | external_llvm-8190173350f4e4d916d2307278955b133fba8a00.zip external_llvm-8190173350f4e4d916d2307278955b133fba8a00.tar.gz external_llvm-8190173350f4e4d916d2307278955b133fba8a00.tar.bz2 | |
For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the
words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements
instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107890 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMBaseInstrInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index f053e81..902a29c 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -848,7 +848,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { // FIXME: It's possible to only store part of the QQ register if the // spilled def has a sub-register index. - MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST2q32)) + MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VST1d64Q)) .addFrameIndex(FI).addImm(16); MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI); MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI); @@ -941,7 +941,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, case ARM::QQPRRegClassID: case ARM::QQPR_VFP2RegClassID: if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) { - MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD2q32)); + MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLD1d64Q)); MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::Define, TRI); MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::Define, TRI); MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::Define, TRI); |