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authorBenjamin Kramer <benny.kra@googlemail.com>2013-06-27 11:07:42 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2013-06-27 11:07:42 +0000
commit872bb3681009ab31965228305bc0452e84569355 (patch)
tree159cb659e138e3883e847f98fed86bedac566ee4 /lib/Target
parent88a9e6a0b313164009a32d7712c4dc95beb4bead (diff)
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Don't cast away constness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185071 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/X86/X86ISelDAGToDAG.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 39b205e..b079281 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -500,7 +500,8 @@ void X86DAGToDAGISel::PreprocessISelDAG() {
// If the source and destination are SSE registers, then this is a legal
// conversion that should not be lowered.
- X86TargetLowering *X86Lowering = (X86TargetLowering*)getTargetLowering();
+ const X86TargetLowering *X86Lowering =
+ static_cast<const X86TargetLowering *>(getTargetLowering());
bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
if (SrcIsSSE && DstIsSSE)