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| author | Nadav Rotem <nadav.rotem@intel.com> | 2012-05-19 20:30:08 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2012-05-19 20:30:08 +0000 |
| commit | 87d35e8c715f5116b072ef8fd742c0cfb6fb5ce4 (patch) | |
| tree | e87b7d6b3b1ae7bd578bc3912652633bd1775590 /lib/Target | |
| parent | 4fc8a5de44c2fc3ce82d5467bd96dfe25aa3a0e9 (diff) | |
| download | external_llvm-87d35e8c715f5116b072ef8fd742c0cfb6fb5ce4.zip external_llvm-87d35e8c715f5116b072ef8fd742c0cfb6fb5ce4.tar.gz external_llvm-87d35e8c715f5116b072ef8fd742c0cfb6fb5ce4.tar.bz2 | |
On Haswell, perfer storing YMM registers using a single instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157129 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 203c873..2810f42 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -14532,13 +14532,12 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI = DAG.getTargetLoweringInfo(); // If we are saving a concatenation of two XMM registers, perform two stores. - // This is better in Sandy Bridge cause one 256-bit mem op is done via two - // 128-bit ones. If in the future the cost becomes only one memory access the - // first version would be better. - if (VT.getSizeInBits() == 256 && + // On Sandy Bridge, 256-bit memory operations are executed by two + // 128-bit ports. However, on Haswell it is better to issue a single 256-bit + // memory operation. + if (VT.getSizeInBits() == 256 && !Subtarget->hasAVX2() && StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && StoredVal.getNumOperands() == 2) { - SDValue Value0 = StoredVal.getOperand(0); SDValue Value1 = StoredVal.getOperand(1); |