Added a few tweaks to the Intel Descriptor-table support instructions to allow

word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 48 insertions, 0 deletions

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index c9e2107..4aad817 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -1089,6 +1089,46 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
     Operands.push_back(X86Operand::CreateImm(A, NameLoc, NameLoc));
   }
 
+  // "lgdtl" is not ambiguous 32-bit mode and is the same as "lgdt".
+  // "lgdtq" is not ambiguous 64-bit mode and is the same as "lgdt".
+  if ((Name == "lgdtl" && Is64Bit == false) ||
+      (Name == "lgdtq" && Is64Bit == true)) {
+    const char *NewName = "lgdt";
+    delete Operands[0];
+    Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
+    Name = NewName;
+  }
+
+  // "lidtl" is not ambiguous 32-bit mode and is the same as "lidt".
+  // "lidtq" is not ambiguous 64-bit mode and is the same as "lidt".
+  if ((Name == "lidtl" && Is64Bit == false) ||
+      (Name == "lidtq" && Is64Bit == true)) {
+    const char *NewName = "lidt";
+    delete Operands[0];
+    Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
+    Name = NewName;
+  }
+
+  // "sgdtl" is not ambiguous 32-bit mode and is the same as "sgdt".
+  // "sgdtq" is not ambiguous 64-bit mode and is the same as "sgdt".
+  if ((Name == "sgdtl" && Is64Bit == false) ||
+      (Name == "sgdtq" && Is64Bit == true)) {
+    const char *NewName = "sgdt";
+    delete Operands[0];
+    Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
+    Name = NewName;
+  }
+
+  // "sidtl" is not ambiguous 32-bit mode and is the same as "sidt".
+  // "sidtq" is not ambiguous 64-bit mode and is the same as "sidt".
+  if ((Name == "sidtl" && Is64Bit == false) ||
+      (Name == "sidtq" && Is64Bit == true)) {
+    const char *NewName = "sidt";
+    delete Operands[0];
+    Operands[0] = X86Operand::CreateToken(NewName, NameLoc);
+    Name = NewName;
+  }
+
   return false;
 }
 
diff --git a/lib/Target/X86/X86InstrSystem.td b/lib/Target/X86/X86InstrSystem.td
index 2d27209..48b6d6e 100644
--- a/lib/Target/X86/X86InstrSystem.td
+++ b/lib/Target/X86/X86InstrSystem.td
@@ -321,8 +321,12 @@ def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
 //===----------------------------------------------------------------------===//
 // Descriptor-table support instructions
 
+def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
+              "sgdtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
               "sgdt\t$dst", []>, TB;
+def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
+              "sidtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
               "sidt\t$dst", []>, TB;
 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
@@ -339,8 +343,12 @@ def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
                  "sldt{q}\t$dst", []>, TB;
 
+def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
+              "lgdtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
               "lgdt\t$src", []>, TB;
+def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
+              "lidtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
               "lidt\t$src", []>, TB;
 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),