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authorScott Michel <scottm@aero.org>2008-12-04 17:16:59 +0000
committerScott Michel <scottm@aero.org>2008-12-04 17:16:59 +0000
commit8c2746e27f5dc52c0e7f599e8889103a2a8ecf7d (patch)
tree98a2ef0246c97b2fae4042ea873d4f5a60adc455 /lib/Target
parentd234e79bf663766a02334c61c4b8212b9553f065 (diff)
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Missing closing brace and reverse conditional condition on NDEBUG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60541 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.cpp10
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index a08ee87..17d88a9 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -766,7 +766,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
LN->getSrcValue(), LN->getSrcValueOffset(),
LN->isVolatile(), LN->getAlignment());
-#if 0 && defined(NDEBUG)
+#if 0 && !defined(NDEBUG)
if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
const SDValue &currentRoot = DAG.getRoot();
@@ -3021,7 +3021,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
SDValue combinedConst =
DAG.getConstant(CN0->getZExtValue() + CN1->getZExtValue(), Op0VT);
-#if defined(NDEBUG)
+#if !defined(NDEBUG)
if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
cerr << "\n"
<< "Replace: (add " << CN0->getZExtValue() << ", "
@@ -3064,14 +3064,14 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
// (any_extend (SPUextract_elt0 <arg>)) ->
// (SPUextract_elt0 <arg>)
// Types must match, however...
-#if defined(NDEBUG)
- // if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
+#if !defined(NDEBUG)
+ if (DebugFlag && isCurrentDebugType(DEBUG_TYPE)) {
cerr << "\nReplace: ";
N->dump(&DAG);
cerr << "\nWith: ";
Op0.getNode()->dump(&DAG);
cerr << "\n";
-
+ }
#endif
return Op0;