- Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency.

- Add test pattern matching in CellSPU's icmp32.ll test harness
- Fix CellSPU fcmp.ll-generated assert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48197 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 10 insertions, 10 deletions

diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index a6c0b87..2922609 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -122,9 +122,6 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
   setUseUnderscoreLongJmp(true);
     
   // Set up the SPU's register classes:
-  // NOTE: i8 register class is not registered because we cannot determine when
-  // we need to zero or sign extend for custom-lowered loads and stores.
-  // NOTE: Ignore the previous note. For now. :-)
   addRegisterClass(MVT::i8,   SPU::R8CRegisterClass);
   addRegisterClass(MVT::i16,  SPU::R16CRegisterClass);
   addRegisterClass(MVT::i32,  SPU::R32CRegisterClass);
@@ -243,22 +240,19 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM)
 
   setOperationAction(ISD::CTLZ , MVT::i32,   Legal);
   
-  // SPU has a version of select
+  // SPU has a version of select that implements (a&~c)|(b|c), just like
+  // select ought to work:
   setOperationAction(ISD::SELECT, MVT::i1,   Promote);
   setOperationAction(ISD::SELECT, MVT::i8,   Legal);
   setOperationAction(ISD::SELECT, MVT::i16,  Legal);
   setOperationAction(ISD::SELECT, MVT::i32,  Legal);
   setOperationAction(ISD::SELECT, MVT::i64,  Expand);
-  setOperationAction(ISD::SELECT, MVT::f32,  Expand);
-  setOperationAction(ISD::SELECT, MVT::f64,  Expand);
 
   setOperationAction(ISD::SETCC, MVT::i1,    Promote);
   setOperationAction(ISD::SETCC, MVT::i8,    Legal);
   setOperationAction(ISD::SETCC, MVT::i16,   Legal);
   setOperationAction(ISD::SETCC, MVT::i32,   Legal);
   setOperationAction(ISD::SETCC, MVT::i64,   Expand);
-  setOperationAction(ISD::SETCC, MVT::f32,   Expand);
-  setOperationAction(ISD::SETCC, MVT::f64,   Expand);
 
   // Zero extension and sign extension for i64 have to be
   // custom legalized
@@ -449,7 +443,11 @@ SPUTargetLowering::getTargetNodeName(unsigned Opcode) const
 
 MVT::ValueType
 SPUTargetLowering::getSetCCResultType(const SDOperand &Op) const {
-  return Op.getValueType();
+  MVT::ValueType VT = Op.getValueType();
+  if (MVT::isInteger(VT))
+    return VT;
+  else
+    return MVT::i32;
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/IA64/IA64ISelLowering.h b/lib/Target/IA64/IA64ISelLowering.h
index d0cf2a9..aef51f0 100644
--- a/lib/Target/IA64/IA64ISelLowering.h
+++ b/lib/Target/IA64/IA64ISelLowering.h
@@ -47,7 +47,9 @@ namespace llvm {
     unsigned VirtGPR; // this is public so it can be accessed in the selector
                       // for ISD::RET. add an accessor instead? FIXME
     const char *getTargetNodeName(unsigned Opcode) const;
-    MVT::ValueType getSetCCResultType(const SDOperand &) const;
+
+    /// getSetCCResultType: return ISD::SETCC's result type.
+    virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
       
     /// LowerArguments - This hook must be implemented to indicate how we should
     /// lower the arguments for the specified function, into the specified DAG.