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| author | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-10-18 22:36:26 +0000 |
|---|---|---|
| committer | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-10-18 22:36:26 +0000 |
| commit | 97b8b4410a43bfef4e09a8db855e671b5013d060 (patch) | |
| tree | cb52fc1a5fb46df00a4b3b8d19fd48987d1e20b4 /lib/Target | |
| parent | f8f2afb8cc5f080b291faad678e0a256ea44d15f (diff) | |
| download | external_llvm-97b8b4410a43bfef4e09a8db855e671b5013d060.zip external_llvm-97b8b4410a43bfef4e09a8db855e671b5013d060.tar.gz external_llvm-97b8b4410a43bfef4e09a8db855e671b5013d060.tar.bz2 | |
removed some debug messages
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@910 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp | 32 |
1 files changed, 17 insertions, 15 deletions
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp index 253370e..acf6585 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp @@ -256,7 +256,7 @@ void PhyRegAlloc::addInterferencesForArgs() addInterference( *ArgIt, InSet, false ); // add interferences between // args and LVars at start if( DEBUG_RA > 1) { - cout << " - %% adding interference for argument "; + cout << " - %% adding interference for argument "; printValue( (const Value *) *ArgIt); cout << endl; } } @@ -326,7 +326,7 @@ void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst, // if the value is in both LV sets (i.e., live before and after // the call machine instruction) - + unsigned Reg = MRI.getUnifiedRegNum(RCID, Color); if( PushedRegSet.find(Reg) == PushedRegSet.end() ) { @@ -350,8 +350,12 @@ void PhyRegAlloc::insertCallerSavingCode(const MachineInstr *MInst, PushedRegSet.insert( Reg ); StackOff -= 8; // ****TODO: Correct ?????? - cerr << "\n $$$ Inserted caller saving instr"; - + + if(DEBUG_RA) { + cout << "For callee save call inst:" << *MInst << endl; + cerr << "\n -inserted caller saving instrs:\n\t "; + cerr << *AdIBef << "\n\t" << *AdIAft ; + } } // if not already pushed } // if LR has a volatile color @@ -405,10 +409,9 @@ void PhyRegAlloc::updateMachineCode() for( AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt ) { - cerr << " *$* PREPENDed instr opcode: "; - cerr << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString; - cerr << endl; - + if( DEBUG_RA) + cerr << " *$* PREPENDed instr " << *AdIt << endl; + MInstIterator = MIVec.insert( MInstIterator, *AdIt ); ++MInstIterator; } @@ -513,10 +516,9 @@ void PhyRegAlloc::updateMachineCode() for( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) { - cerr << " *#* APPENDed instr opcode: "; - cerr << TargetInstrDescriptors[(*AdIt)->getOpCode()].opCodeString; - cerr << endl; - + if(DEBUG_RA) + cerr << " *#* APPENDed instr opcode: " << *AdIt << endl; + MInstIterator = MIVec.insert( MInstIterator, *AdIt ); ++MInstIterator; } @@ -574,8 +576,8 @@ void PhyRegAlloc::printMachineCode() MachineOperand& Op = MInst->getOperand(OpNum); if( Op.getOperandType() == MachineOperand::MO_VirtualRegister || - Op.getOperandType() == MachineOperand::MO_CCRegister || - Op.getOperandType() == MachineOperand::MO_PCRelativeDisp ) { + Op.getOperandType() == MachineOperand::MO_CCRegister /*|| + Op.getOperandType() == MachineOperand::MO_PCRelativeDisp*/ ) { const Value *const Val = Op.getVRegValue () ; // ****this code is temporary till NULL Values are fixed @@ -751,7 +753,7 @@ void PhyRegAlloc::allocateRegisters() colorIncomingArgs(); colorCallRetArgs(); - + updateMachineCode(); if (DEBUG_RA) { PrintMachineInstructions(Meth); |