diff options
author | Andrew Lenharth <andrewl@lenharth.org> | 2005-07-28 18:14:47 +0000 |
---|---|---|
committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-07-28 18:14:47 +0000 |
commit | 98169be50bbec4cd3406c7e6557c8661764f2a94 (patch) | |
tree | 8269420c0d6f43a0afdae822fd30389f66dd1397 /lib/Target | |
parent | fe660397e14ecba84e792ada489f2bda7269b413 (diff) | |
download | external_llvm-98169be50bbec4cd3406c7e6557c8661764f2a94.zip external_llvm-98169be50bbec4cd3406c7e6557c8661764f2a94.tar.gz external_llvm-98169be50bbec4cd3406c7e6557c8661764f2a94.tar.bz2 |
support bsr, and more .td simplification
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22543 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/Alpha/AlphaCodeEmitter.cpp | 3 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 24 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaInstrFormats.td | 16 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.td | 64 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaJITInfo.cpp | 16 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaRelocations.h | 1 |
6 files changed, 76 insertions, 48 deletions
diff --git a/lib/Target/Alpha/AlphaCodeEmitter.cpp b/lib/Target/Alpha/AlphaCodeEmitter.cpp index 8bd8766..a4e9e03 100644 --- a/lib/Target/Alpha/AlphaCodeEmitter.cpp +++ b/lib/Target/Alpha/AlphaCodeEmitter.cpp @@ -180,6 +180,9 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) { int Offset = 0; bool useGOT = false; switch (MI.getOpcode()) { + case Alpha::BSR: + Reloc = Alpha::reloc_bsr; + break; case Alpha::LDLr: case Alpha::LDQr: case Alpha::LDBUr: diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index e3c5c4b..1af8aa6 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -859,7 +859,7 @@ void AlphaISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble) unsigned Opc; if (EnableAlphaFTOI) { Opc = isDouble ? Alpha::FTOIT : Alpha::FTOIS; - BuildMI(BB, Opc, 1, dst).addReg(src); + BuildMI(BB, Opc, 1, dst).addReg(src).addReg(Alpha::F31); } else { //The hard way: // Spill the integer to memory and reload it from there. @@ -886,7 +886,7 @@ void AlphaISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble) unsigned Opc; if (EnableAlphaFTOI) { Opc = isDouble?Alpha::ITOFT:Alpha::ITOFS; - BuildMI(BB, Opc, 1, dst).addReg(src); + BuildMI(BB, Opc, 1, dst).addReg(src).addReg(Alpha::R31); } else { //The hard way: // Spill the integer to memory and reload it from there. @@ -946,7 +946,7 @@ bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst) //assert(0 && "Setcc On float?\n"); std::cerr << "Setcc on float!\n"; Tmp3 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp1); + BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp1); Tmp1 = Tmp3; } if (SetCC->getOperand(1).getValueType() == MVT::f32) @@ -954,7 +954,7 @@ bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst) //assert (0 && "Setcc On float?\n"); std::cerr << "Setcc on float!\n"; Tmp3 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Tmp2); + BuildMI(BB, Alpha::CVTST, 1, Tmp3).addReg(Alpha::F31).addReg(Tmp2); Tmp2 = Tmp3; } @@ -1447,10 +1447,10 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { Tmp2 = SelectExpr(N.getOperand(0).getOperand(1)); MoveInt2FP(Tmp1, Tmp4, true); MoveInt2FP(Tmp2, Tmp5, true); - BuildMI(BB, Alpha::CVTQT, 1, Tmp6).addReg(Tmp4); - BuildMI(BB, Alpha::CVTQT, 1, Tmp7).addReg(Tmp5); + BuildMI(BB, Alpha::CVTQT, 1, Tmp6).addReg(Alpha::F31).addReg(Tmp4); + BuildMI(BB, Alpha::CVTQT, 1, Tmp7).addReg(Alpha::F31).addReg(Tmp5); BuildMI(BB, Alpha::DIVT, 2, Tmp8).addReg(Tmp6).addReg(Tmp7); - BuildMI(BB, Alpha::CVTTQ, 1, Tmp9).addReg(Tmp8); + BuildMI(BB, Alpha::CVTTQ, 1, Tmp9).addReg(Alpha::F31).addReg(Tmp8); MoveFP2Int(Tmp9, Result, true); return Result; } @@ -1925,11 +1925,11 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { if (SrcType == MVT::f32) { Tmp2 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Tmp1); + BuildMI(BB, Alpha::CVTST, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1); Tmp1 = Tmp2; } Tmp2 = MakeReg(MVT::f64); - BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Tmp1); + BuildMI(BB, Alpha::CVTTQ, 1, Tmp2).addReg(Alpha::F31).addReg(Tmp1); MoveFP2Int(Tmp2, Result, true); return Result; @@ -2153,7 +2153,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { N.getOperand(0).getValueType() == MVT::f64 && "only f64 to f32 conversion supported here"); Tmp1 = SelectExpr(N.getOperand(0)); - BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Tmp1); + BuildMI(BB, Alpha::CVTTS, 1, Result).addReg(Alpha::F31).addReg(Tmp1); return Result; case ISD::FP_EXTEND: @@ -2161,7 +2161,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { N.getOperand(0).getValueType() == MVT::f32 && "only f32 to f64 conversion supported here"); Tmp1 = SelectExpr(N.getOperand(0)); - BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1); + BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Alpha::F31).addReg(Tmp1); return Result; case ISD::ConstantFP: @@ -2186,7 +2186,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { Tmp2 = MakeReg(MVT::f64); MoveInt2FP(Tmp1, Tmp2, true); Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS; - BuildMI(BB, Opc, 1, Result).addReg(Tmp2); + BuildMI(BB, Opc, 1, Result).addReg(Alpha::F31).addReg(Tmp2); return Result; } } diff --git a/lib/Target/Alpha/AlphaInstrFormats.td b/lib/Target/Alpha/AlphaInstrFormats.td index abf2409..f01e907 100644 --- a/lib/Target/Alpha/AlphaInstrFormats.td +++ b/lib/Target/Alpha/AlphaInstrFormats.td @@ -153,11 +153,25 @@ class OcmFormL<bits<6> opcode, bits<7> fun, dag OL, string asmstr> } //3.3.4 -class FPForm<bits<6> opcode, bits<11> fun, dag OL, string asmstr> : InstAlpha<opcode, OL, asmstr> { +class FPForm<bits<6> opcode, bits<11> fun, string asmstr> + : InstAlpha<opcode, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), asmstr> { + bits<5> Fc; bits<5> Fa; bits<5> Fb; bits<11> Function = fun; + + let Inst{25-21} = Fa; + let Inst{20-16} = Fb; + let Inst{15-5} = Function; + let Inst{4-0} = Fc; +} + +class FPFormCM<bits<6> opcode, bits<11> fun, dag OL, string asmstr> + : InstAlpha<opcode, OL, asmstr> { bits<5> Fc; + bits<5> Fa; + bits<5> Fb; + bits<11> Function = fun; let Inst{25-21} = Fa; let Inst{20-16} = Fb; diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index a238d2e..b1b6d35 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -98,17 +98,17 @@ let isTwoAddress = 1 in { "cmovne $RCOND,$L,$RDEST">; //CMOVE if RCOND != zero //conditional moves, fp - def FCMOVEQ : FPForm<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), + def FCMOVEQ : FPFormCM<0x17, 0x02A, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmoveq $RCOND,$RSRC,$RDEST">; //FCMOVE if = zero - def FCMOVGE : FPForm<0x17, 0x02D, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), + def FCMOVGE : FPFormCM<0x17, 0x02D, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovge $RCOND,$RSRC,$RDEST">; //FCMOVE if >= zero - def FCMOVGT : FPForm<0x17, 0x02F, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), + def FCMOVGT : FPFormCM<0x17, 0x02F, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovgt $RCOND,$RSRC,$RDEST">; //FCMOVE if > zero - def FCMOVLE : FPForm<0x17, 0x02E, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), + def FCMOVLE : FPFormCM<0x17, 0x02E, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovle $RCOND,$RSRC,$RDEST">; //FCMOVE if <= zero - def FCMOVLT : FPForm<0x17, 0x02, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), + def FCMOVLT : FPFormCM<0x17, 0x02, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovlt $RCOND,$RSRC,$RDEST">; // FCMOVE if < zero - def FCMOVNE : FPForm<0x17, 0x02B, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), + def FCMOVNE : FPFormCM<0x17, 0x02B, (ops FPRC:$RDEST, FPRC:$RSRC2, FPRC:$RSRC, FPRC:$RCOND), "fcmovne $RCOND,$RSRC,$RDEST">; //FCMOVE if != zero } @@ -232,10 +232,10 @@ def CMPULT : OForm< 0x10, 0x1D, "cmpult $RA,$RB,$RC">; //Compare unsigned quad def CMPULTi : OFormL<0x10, 0x1D, "cmpult $RA,$L,$RC">; //Compare unsigned quadword less than //Comparison, FP -def CMPTEQ : FPForm<0x16, 0x0A5, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal -def CMPTLE : FPForm<0x16, 0x0A7, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptle/su $RA,$RB,$RC">; //Compare T_floating less than or equal -def CMPTLT : FPForm<0x16, 0x0A6, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptlt/su $RA,$RB,$RC">; //Compare T_floating less than -def CMPTUN : FPForm<0x16, 0x0A4, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered +def CMPTEQ : FPForm<0x16, 0x0A5, "cmpteq/su $RA,$RB,$RC">; //Compare T_floating equal +def CMPTLE : FPForm<0x16, 0x0A7, "cmptle/su $RA,$RB,$RC">; //Compare T_floating less than or equal +def CMPTLT : FPForm<0x16, 0x0A6, "cmptlt/su $RA,$RB,$RC">; //Compare T_floating less than +def CMPTUN : FPForm<0x16, 0x0A4, "cmptun/su $RA,$RB,$RC">; //Compare T_floating unordered //There are in the Multimedia extentions, so let's not use them yet def MAXSB8 : OForm<0x1C, 0x3E, "MAXSB8 $RA,$RB,$RC">; //Vector signed byte maximum @@ -350,37 +350,37 @@ def FBLT : FBForm<0x32, "fblt $RA,$DISP">; //Floating branch if < zero def FBNE : FBForm<0x35, "fbne $RA,$DISP">; //Floating branch if != zero //Funky Floating point ops -def CPYS : FPForm<0x17, 0x020, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpys $RA,$RB,$RC">; //Copy sign -def CPYSE : FPForm<0x17, 0x022, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpyse $RA,$RB,$RC">; //Copy sign and exponent -def CPYSN : FPForm<0x17, 0x021, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "cpysn $RA,$RB,$RC">; //Copy sign negate +def CPYS : FPForm<0x17, 0x020, "cpys $RA,$RB,$RC">; //Copy sign +def CPYSE : FPForm<0x17, 0x022, "cpyse $RA,$RB,$RC">; //Copy sign and exponent +def CPYSN : FPForm<0x17, 0x021, "cpysn $RA,$RB,$RC">; //Copy sign negate //Basic Floating point ops -def ADDS : FPForm<0x16, 0x080, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "adds/su $RA,$RB,$RC">; //Add S_floating -def ADDT : FPForm<0x16, 0x0A0, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "addt/su $RA,$RB,$RC">; //Add T_floating -def SUBS : FPForm<0x16, 0x081, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subs/su $RA,$RB,$RC">; //Subtract S_floating -def SUBT : FPForm<0x16, 0x0A1, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "subt/su $RA,$RB,$RC">; //Subtract T_floating -def DIVS : FPForm<0x16, 0x083, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divs/su $RA,$RB,$RC">; //Divide S_floating -def DIVT : FPForm<0x16, 0x0A3, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "divt/su $RA,$RB,$RC">; //Divide T_floating -def MULS : FPForm<0x16, 0x082, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "muls/su $RA,$RB,$RC">; //Multiply S_floating -def MULT : FPForm<0x16, 0x0A2, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "mult/su $RA,$RB,$RC">; //Multiply T_floating -def SQRTS : FPForm<0x14, 0x08B, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "sqrts $RA,$RB,$RC">; //Square root S_floating -def SQRTT : FPForm<0x14, 0x0AB, (ops FPRC:$RC, FPRC:$RA, FPRC:$RB), "sqrtt $RA,$RB,$RC">; //Square root T_floating +def ADDS : FPForm<0x16, 0x080, "adds/su $RA,$RB,$RC">; //Add S_floating +def ADDT : FPForm<0x16, 0x0A0, "addt/su $RA,$RB,$RC">; //Add T_floating +def SUBS : FPForm<0x16, 0x081, "subs/su $RA,$RB,$RC">; //Subtract S_floating +def SUBT : FPForm<0x16, 0x0A1, "subt/su $RA,$RB,$RC">; //Subtract T_floating +def DIVS : FPForm<0x16, 0x083, "divs/su $RA,$RB,$RC">; //Divide S_floating +def DIVT : FPForm<0x16, 0x0A3, "divt/su $RA,$RB,$RC">; //Divide T_floating +def MULS : FPForm<0x16, 0x082, "muls/su $RA,$RB,$RC">; //Multiply S_floating +def MULT : FPForm<0x16, 0x0A2, "mult/su $RA,$RB,$RC">; //Multiply T_floating +def SQRTS : FPForm<0x14, 0x08B, "sqrts $RA,$RB,$RC">; //Square root S_floating +def SQRTT : FPForm<0x14, 0x0AB, "sqrtt $RA,$RB,$RC">; //Square root T_floating //INT reg to FP reg and back again //not supported on 21164 -def FTOIS : FPForm<0x1C, 0x078, (ops FPRC:$RC, GPRC:$RA), "ftois $RA,$RC">; //Floating to integer move, S_floating -def FTOIT : FPForm<0x1C, 0x070, (ops FPRC:$RC, GPRC:$RA), "ftoit $RA,$RC">; //Floating to integer move, T_floating -def ITOFS : FPForm<0x14, 0x004, (ops FPRC:$RC, GPRC:$RA), "itofs $RA,$RC">; //Integer to floating move, S_floating -def ITOFT : FPForm<0x14, 0x024, (ops FPRC:$RC, GPRC:$RA), "itoft $RA,$RC">; //Integer to floating move, T_floating +def FTOIS : FPForm<0x1C, 0x078, "ftois $RA,$RC">; //Floating to integer move, S_floating +def FTOIT : FPForm<0x1C, 0x070, "ftoit $RA,$RC">; //Floating to integer move, T_floating +def ITOFS : FPForm<0x14, 0x004, "itofs $RA,$RC">; //Integer to floating move, S_floating +def ITOFT : FPForm<0x14, 0x024, "itoft $RA,$RC">; //Integer to floating move, T_floating //CVTLQ F-P 17.010 Convert longword to quadword //CVTQL F-P 17.030 Convert quadword to longword //These use SW completion, may not have function code for that set right (matters for JIT) -def CVTQS : FPForm<0x16, 0x0BC, (ops FPRC:$RC, FPRC:$RA), "cvtqs $RA,$RC">; //Convert quadword to S_floating -def CVTQT : FPForm<0x16, 0x0BE, (ops FPRC:$RC, FPRC:$RA), "cvtqt $RA,$RC">; //Convert quadword to T_floating -def CVTST : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtsts $RA,$RC">; //Convert S_floating to T_floating -def CVTTQ : FPForm<0x16, 0x0AF, (ops FPRC:$RC, FPRC:$RA), "cvttq/svc $RA,$RC">; //Convert T_floating to quadword -def CVTTS : FPForm<0x16, 0x2AC, (ops FPRC:$RC, FPRC:$RA), "cvtts/su $RA,$RC">; //Convert T_floating to S_floating +def CVTQS : FPForm<0x16, 0x0BC, "cvtqs $RB,$RC">; //Convert quadword to S_floating +def CVTQT : FPForm<0x16, 0x0BE, "cvtqt $RB,$RC">; //Convert quadword to T_floating +def CVTST : FPForm<0x16, 0x2AC, "cvtsts $RB,$RC">; //Convert S_floating to T_floating +def CVTTQ : FPForm<0x16, 0x0AF, "cvttq/svc $RB,$RC">; //Convert T_floating to quadword +def CVTTS : FPForm<0x16, 0x2AC, "cvtts/su $RB,$RC">; //Convert T_floating to S_floating //S_floating : IEEE Single //T_floating : IEEE Double diff --git a/lib/Target/Alpha/AlphaJITInfo.cpp b/lib/Target/Alpha/AlphaJITInfo.cpp index 3fae43c..0f7e4f3 100644 --- a/lib/Target/Alpha/AlphaJITInfo.cpp +++ b/lib/Target/Alpha/AlphaJITInfo.cpp @@ -245,6 +245,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR, for (unsigned i = 0; i != NumRelocs; ++i, ++MR) { unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4; long idx = 0; + bool doCommon = true; switch ((Alpha::RelocationType)MR->getRelocationType()) { default: assert(0 && "Unknown relocation type!"); case Alpha::reloc_literal: @@ -289,9 +290,18 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR, assert(0 && "Cannot handle gpdist yet"); } break; + case Alpha::reloc_bsr: { + idx = (((unsigned char*)MR->getResultPointer() - + (unsigned char*)RelocPos) >> 2) + 1; //skip first 2 inst of fun + *RelocPos |= (idx & ((1 << 21)-1)); + doCommon = false; + break; + } + } + if (doCommon) { + short x = (short)idx; + assert(x == idx); + *(short*)RelocPos = x; } - short x = (short)idx; - assert(x == idx); - *(short*)RelocPos = x; } } diff --git a/lib/Target/Alpha/AlphaRelocations.h b/lib/Target/Alpha/AlphaRelocations.h index f913c9b..59b9765 100644 --- a/lib/Target/Alpha/AlphaRelocations.h +++ b/lib/Target/Alpha/AlphaRelocations.h @@ -23,6 +23,7 @@ namespace llvm { reloc_gprellow, reloc_gprelhigh, reloc_gpdist, + reloc_bsr, }; } } |