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| author | Shih-wei Liao <sliao@google.com> | 2010-05-26 00:25:05 +0000 |
|---|---|---|
| committer | Shih-wei Liao <sliao@google.com> | 2010-05-26 00:25:05 +0000 |
| commit | ac79ed164b7f70ab2f16557c7d4eed7e9db3063a (patch) | |
| tree | 625a9bd0012af8165a6206cd49dd3ce58ba36798 /lib/Target | |
| parent | 521a8d4fa73593c22976fc4ad509d46840ef512b (diff) | |
| download | external_llvm-ac79ed164b7f70ab2f16557c7d4eed7e9db3063a.zip external_llvm-ac79ed164b7f70ab2f16557c7d4eed7e9db3063a.tar.gz external_llvm-ac79ed164b7f70ab2f16557c7d4eed7e9db3063a.tar.bz2 | |
Adding the missing implementation of Bitfield's "clear" and "insert".
Fixing http://llvm.org/bugs/show_bug.cgi?id=7222.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104653 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMCodeEmitter.cpp | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index eaf4760..66c8032 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -781,10 +781,6 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, unsigned ImplicitRn) { const TargetInstrDesc &TID = MI.getDesc(); - if (TID.Opcode == ARM::BFC) { - report_fatal_error("ARMv6t2 JIT is not yet supported."); - } - // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -820,6 +816,15 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, Binary |= ((Hi16 >> 12) & 0xF) << 16; emitWordLE(Binary); return; + } else if((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) { + uint32_t v = ~MI.getOperand(2).getImm(); + int32_t lsb = CountTrailingZeros_32(v); + int32_t msb = (32 - CountLeadingZeros_32(v)) - 1; + // Insts[20-16] = msb, Insts[11-7] = lsb + Binary |= (msb & 0x1F) << 16; + Binary |= (lsb & 0x1F) << 7; + emitWordLE(Binary); + return; } // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. |