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authorEvan Cheng <evan.cheng@apple.com>2009-06-19 07:06:07 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-06-19 07:06:07 +0000
commitb1019480b6806c38432ad3357ae7d756573c0835 (patch)
tree888acc536652c6e802ec406631df48deaab8aa5c /lib/Target
parent7e2242be71bc44ab1447b5211b3c0f1cec94c467 (diff)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73761 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 345f172..2443625 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -294,6 +294,10 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
if (!Subtarget->isThumb()) {
// Use branch latency information to determine if-conversion limits.
+ // FIXME: If-converter should use instruction latency of the branch being
+ // eliminated to compute the threshold. For ARMv6, the branch "latency"
+ // varies depending on whether it's dynamically or statically predicted
+ // and on whether the destination is in the prefetch buffer.
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
const InstrItineraryData &InstrItins = Subtarget->getInstrItineraryData();
unsigned Latency= InstrItins.getLatency(TII->get(ARM::Bcc).getSchedClass());