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| author | Jim Grosbach <grosbach@apple.com> | 2011-07-22 20:11:20 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-07-22 20:11:20 +0000 |
| commit | b206daaec1a2ec25e99fbdc413cd0866cec160b2 (patch) | |
| tree | 014251e66d7b5142ee05fac4847138ea379fe17d /lib/Target | |
| parent | 0ffd4a09dfb1ee56ec335fed0d15954f92cfa5b3 (diff) | |
| download | external_llvm-b206daaec1a2ec25e99fbdc413cd0866cec160b2.zip external_llvm-b206daaec1a2ec25e99fbdc413cd0866cec160b2.tar.gz external_llvm-b206daaec1a2ec25e99fbdc413cd0866cec160b2.tar.bz2 | |
ARM encoding and assembly parsing of SMLAD{X} instructions.
Fix encoding of destination register. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135796 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index fb82235..009f7ad 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -3209,14 +3209,14 @@ class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops, : AI<oops, iops, MulFrm, itin, opc, asm, []>, Requires<[IsARM, HasV6]> { bits<4> Rn; bits<4> Rm; - let Inst{4} = 1; - let Inst{5} = swap; - let Inst{6} = sub; - let Inst{7} = 0; - let Inst{21-20} = 0b00; - let Inst{22} = long; let Inst{27-23} = 0b01110; + let Inst{22} = long; + let Inst{21-20} = 0b00; let Inst{11-8} = Rm; + let Inst{7} = 0; + let Inst{6} = sub; + let Inst{5} = swap; + let Inst{4} = 1; let Inst{3-0} = Rn; } class AMulDualI<bit long, bit sub, bit swap, dag oops, dag iops, @@ -3230,6 +3230,8 @@ class AMulDualIa<bit long, bit sub, bit swap, dag oops, dag iops, InstrItinClass itin, string opc, string asm> : AMulDualIbase<long, sub, swap, oops, iops, itin, opc, asm> { bits<4> Ra; + bits<4> Rd; + let Inst{19-16} = Rd; let Inst{15-12} = Ra; } class AMulDualI64<bit long, bit sub, bit swap, dag oops, dag iops, |