diff options
author | Craig Topper <craig.topper@gmail.com> | 2012-03-04 10:16:38 +0000 |
---|---|---|
committer | Craig Topper <craig.topper@gmail.com> | 2012-03-04 10:16:38 +0000 |
commit | b6632ba380cf624e60fe16b03d6e21b05dd07724 (patch) | |
tree | 5b3ca53e138cd22a7b04e0e034b0a952d0972de7 /lib/Target | |
parent | 015f228861ef9b337366f92f637d4e8d624bb006 (diff) | |
download | external_llvm-b6632ba380cf624e60fe16b03d6e21b05dd07724.zip external_llvm-b6632ba380cf624e60fe16b03d6e21b05dd07724.tar.gz external_llvm-b6632ba380cf624e60fe16b03d6e21b05dd07724.tar.bz2 |
Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.cpp | 26 | ||||
-rw-r--r-- | lib/Target/ARM/ARMBaseRegisterInfo.h | 2 | ||||
-rw-r--r-- | lib/Target/TargetRegisterInfo.cpp | 2 |
3 files changed, 15 insertions, 15 deletions
diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp index fd2ed06..d2aff9a 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -290,7 +290,7 @@ ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, /// getRawAllocationOrder - Returns the register allocation order for a /// specified register class with a target-dependent hint. -ArrayRef<unsigned> +ArrayRef<uint16_t> ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC, unsigned HintType, unsigned HintReg, const MachineFunction &MF) const { @@ -299,71 +299,71 @@ ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC, // of register pairs. // No FP, R9 is available. - static const unsigned GPREven1[] = { + static const uint16_t GPREven1[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R9, ARM::R11 }; - static const unsigned GPROdd1[] = { + static const uint16_t GPROdd1[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, ARM::R10 }; // FP is R7, R9 is available. - static const unsigned GPREven2[] = { + static const uint16_t GPREven2[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R9, ARM::R11 }; - static const unsigned GPROdd2[] = { + static const uint16_t GPROdd2[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, ARM::R10 }; // FP is R11, R9 is available. - static const unsigned GPREven3[] = { + static const uint16_t GPREven3[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R9 }; - static const unsigned GPROdd3[] = { + static const uint16_t GPROdd3[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, ARM::R8 }; // No FP, R9 is not available. - static const unsigned GPREven4[] = { + static const uint16_t GPREven4[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, ARM::R11 }; - static const unsigned GPROdd4[] = { + static const uint16_t GPROdd4[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, ARM::R10 }; // FP is R7, R9 is not available. - static const unsigned GPREven5[] = { + static const uint16_t GPREven5[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R10, ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, ARM::R11 }; - static const unsigned GPROdd5[] = { + static const uint16_t GPROdd5[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R11, ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, ARM::R10 }; // FP is R11, R9 is not available. - static const unsigned GPREven6[] = { + static const uint16_t GPREven6[] = { ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 }; - static const unsigned GPROdd6[] = { + static const uint16_t GPROdd6[] = { ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 }; diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.h b/lib/Target/ARM/ARMBaseRegisterInfo.h index ddbcf7a..af79351 100644 --- a/lib/Target/ARM/ARMBaseRegisterInfo.h +++ b/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -119,7 +119,7 @@ public: unsigned getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const; - ArrayRef<unsigned> getRawAllocationOrder(const TargetRegisterClass *RC, + ArrayRef<uint16_t> getRawAllocationOrder(const TargetRegisterClass *RC, unsigned HintType, unsigned HintReg, const MachineFunction &MF) const; diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp index 2689837..1716423 100644 --- a/lib/Target/TargetRegisterInfo.cpp +++ b/lib/Target/TargetRegisterInfo.cpp @@ -71,7 +71,7 @@ TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { /// registers for the specific register class. static void getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R){ - ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF); + ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); for (unsigned i = 0; i != Order.size(); ++i) R.set(Order[i]); } |