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| author | Craig Topper <craig.topper@gmail.com> | 2013-10-14 01:21:22 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2013-10-14 01:21:22 +0000 |
| commit | bae9f69d37a60aad0185cdf17434ec188c976e67 (patch) | |
| tree | ab46de65d6831e972241edf1daa3c8c9576b259d /lib/Target | |
| parent | bf80b3cead9b116ed245ba21552b82c226807586 (diff) | |
| download | external_llvm-bae9f69d37a60aad0185cdf17434ec188c976e67.zip external_llvm-bae9f69d37a60aad0185cdf17434ec188c976e67.tar.gz external_llvm-bae9f69d37a60aad0185cdf17434ec188c976e67.tar.bz2 | |
Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192565 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 6f7e913..90bdfa3 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -2710,6 +2710,7 @@ multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm, !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>, Sched<[WriteVecLogic]>; + let isAsmParserOnly = 1, hasSideEffects = 0 in def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src), !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], IIC_SSE_MOVMSK, d>, REX_W, Sched<[WriteVecLogic]>; @@ -4284,14 +4285,21 @@ def PEXTRWri : PDIi8<0xC5, MRMSrcReg, // Insert let Predicates = [HasAVX] in { defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V; + let isAsmParserOnly = 1, hasSideEffects = 0 in def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, GR64:$src2, i32i8imm:$src3), "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", []>, TB, OpSize, VEX_4V, Sched<[WriteShuffle]>; } -let Constraints = "$src1 = $dst" in - defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>; +let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in { + defm PINSRW : sse2_pinsrw, TB, OpSize; + let isAsmParserOnly = 1, hasSideEffects = 0 in + def PINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst), + (ins VR128:$src1, GR64:$src2, i32i8imm:$src3), + "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", + []>, TB, OpSize, Sched<[WriteShuffle]>; +} // Predicates = [UseSSE2], Constraints = "$src1 = $dst" } // ExeDomain = SSEPackedInt |