diff options
author | Dan Gohman <gohman@apple.com> | 2008-11-18 19:49:32 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2008-11-18 19:49:32 +0000 |
commit | cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2 (patch) | |
tree | edad12015684d0590e53ed853bb0ac5042ae5842 /lib/Target | |
parent | b3b930a011554fc7566dd4311af3862b01e5fd8f (diff) | |
download | external_llvm-cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2.zip external_llvm-cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2.tar.gz external_llvm-cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2.tar.bz2 |
Add more const qualifiers. This fixes build breakage from r59540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMInstrInfo.cpp | 6 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrInfo.h | 6 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 6 | ||||
-rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.h | 6 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.cpp | 6 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.h | 6 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.cpp | 4 | ||||
-rw-r--r-- | lib/Target/Mips/MipsInstrInfo.h | 6 | ||||
-rw-r--r-- | lib/Target/PIC16/PIC16InstrInfo.cpp | 4 | ||||
-rw-r--r-- | lib/Target/PIC16/PIC16InstrInfo.h | 6 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.cpp | 4 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.h | 6 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.cpp | 4 | ||||
-rw-r--r-- | lib/Target/Sparc/SparcInstrInfo.h | 6 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 6 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrInfo.h | 6 | ||||
-rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.cpp | 7 | ||||
-rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.h | 8 |
18 files changed, 63 insertions, 40 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp index 18ab594..e78f2d3 100644 --- a/lib/Target/ARM/ARMInstrInfo.cpp +++ b/lib/Target/ARM/ARMInstrInfo.cpp @@ -73,7 +73,8 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI, } } -unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ +unsigned ARMInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const { switch (MI->getOpcode()) { default: break; case ARM::LDR: @@ -107,7 +108,8 @@ unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) co return 0; } -unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { +unsigned ARMInstrInfo::isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const { switch (MI->getOpcode()) { default: break; case ARM::STR: diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h index 3843860..cdf068f 100644 --- a/lib/Target/ARM/ARMInstrInfo.h +++ b/lib/Target/ARM/ARMInstrInfo.h @@ -160,8 +160,10 @@ public: /// virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const; - virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; - virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; + virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const; + virtual unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const; void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const; diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index b365aba..7b3053e 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -49,7 +49,8 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI, } unsigned -AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const { +AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const { switch (MI->getOpcode()) { case Alpha::LDL: case Alpha::LDQ: @@ -67,7 +68,8 @@ AlphaInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const { } unsigned -AlphaInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { +AlphaInstrInfo::isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const { switch (MI->getOpcode()) { case Alpha::STL: case Alpha::STQ: diff --git a/lib/Target/Alpha/AlphaInstrInfo.h b/lib/Target/Alpha/AlphaInstrInfo.h index abee722..b218873 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.h +++ b/lib/Target/Alpha/AlphaInstrInfo.h @@ -36,8 +36,10 @@ public: virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const; - virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; - virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; + virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const; + virtual unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 29facb9..d10f2b8 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -119,7 +119,8 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI, } unsigned -SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const { +SPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const { switch (MI->getOpcode()) { default: break; case SPU::LQDv16i8: @@ -147,7 +148,8 @@ SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const { } unsigned -SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { +SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const { switch (MI->getOpcode()) { default: break; case SPU::STQDv16i8: diff --git a/lib/Target/CellSPU/SPUInstrInfo.h b/lib/Target/CellSPU/SPUInstrInfo.h index 9c8bcaf..722e1a1 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.h +++ b/lib/Target/CellSPU/SPUInstrInfo.h @@ -43,8 +43,10 @@ namespace llvm { unsigned& sourceReg, unsigned& destReg) const; - unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; - unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; + unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const; + unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const; virtual bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 146c5ca..8d3c5a0 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -75,7 +75,7 @@ isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. unsigned MipsInstrInfo:: -isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const +isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) || (MI->getOpcode() == Mips::LWC1A) || (MI->getOpcode() == Mips::LDC1)) { @@ -96,7 +96,7 @@ isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. unsigned MipsInstrInfo:: -isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const +isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) || (MI->getOpcode() == Mips::SWC1A) || (MI->getOpcode() == Mips::SDC1)) { diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index 31e9cfa..b1c34bc 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -152,14 +152,16 @@ public: /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; + virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const; /// isStoreToStackSlot - If the specified machine instruction is a direct /// store to a stack slot, return the virtual or physical register number of /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; + virtual unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const; /// Branch Analysis virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, diff --git a/lib/Target/PIC16/PIC16InstrInfo.cpp b/lib/Target/PIC16/PIC16InstrInfo.cpp index 96858e3..7cb2379 100644 --- a/lib/Target/PIC16/PIC16InstrInfo.cpp +++ b/lib/Target/PIC16/PIC16InstrInfo.cpp @@ -38,7 +38,7 @@ static bool isZeroImm(const MachineOperand &op) { /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. unsigned PIC16InstrInfo:: -isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const +isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { if (MI->getOpcode() == PIC16::MOVF) { if ((MI->getOperand(2).isFI()) && // is a stack slot @@ -58,7 +58,7 @@ isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. unsigned PIC16InstrInfo:: -isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const +isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { if (MI->getOpcode() == PIC16::MOVWF) { if ((MI->getOperand(0).isFI()) && // is a stack slot diff --git a/lib/Target/PIC16/PIC16InstrInfo.h b/lib/Target/PIC16/PIC16InstrInfo.h index 1e33b0a..250142d 100644 --- a/lib/Target/PIC16/PIC16InstrInfo.h +++ b/lib/Target/PIC16/PIC16InstrInfo.h @@ -40,14 +40,16 @@ public: /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; + virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const; /// isStoreToStackSlot - If the specified machine instruction is a direct /// store to a stack slot, return the virtual or physical register number of /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; + virtual unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const; /// Used for spilling a register void storeRegToStackSlot(MachineBasicBlock &MBB, diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index c275668..87f7b8a 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -98,7 +98,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI, return false; } -unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, +unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { switch (MI->getOpcode()) { default: break; @@ -116,7 +116,7 @@ unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, return 0; } -unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI, +unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { switch (MI->getOpcode()) { default: break; diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index 2e950a3..909b0c5 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -93,8 +93,10 @@ public: unsigned& sourceReg, unsigned& destReg) const; - unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; - unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; + unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const; + unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const; // commuteInstruction - We can commute rlwimi instructions, but only if the // rotate amt is zero. We also have to munge the immediates a bit. diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 47c0672..167012e 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -66,7 +66,7 @@ bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI, /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. -unsigned SparcInstrInfo::isLoadFromStackSlot(MachineInstr *MI, +unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { if (MI->getOpcode() == SP::LDri || MI->getOpcode() == SP::LDFri || @@ -85,7 +85,7 @@ unsigned SparcInstrInfo::isLoadFromStackSlot(MachineInstr *MI, /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. -unsigned SparcInstrInfo::isStoreToStackSlot(MachineInstr *MI, +unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { if (MI->getOpcode() == SP::STri || MI->getOpcode() == SP::STFri || diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h index 7c63316..346be95 100644 --- a/lib/Target/Sparc/SparcInstrInfo.h +++ b/lib/Target/Sparc/SparcInstrInfo.h @@ -54,14 +54,16 @@ public: /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; + virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const; /// isStoreToStackSlot - If the specified machine instruction is a direct /// store to a stack slot, return the virtual or physical register number of /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; + virtual unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const; virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index c08fdd8..fb7793f 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -688,7 +688,7 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, } } -unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI, +unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { switch (MI->getOpcode()) { default: break; @@ -718,7 +718,7 @@ unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI, return 0; } -unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI, +unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { switch (MI->getOpcode()) { default: break; @@ -936,7 +936,7 @@ void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, /// from the argument area of a function if it does not change. This should /// only return true of *all* loads the instruction does are invariant (if it /// does multiple loads). -bool X86InstrInfo::isInvariantLoad(MachineInstr *MI) const { +bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const { // This code cares about loads from three cases: constant pool entries, // invariant argument slots, and global stubs. In order to handle these cases // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index dc76f3e..cf8be96 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -290,14 +290,14 @@ public: // bool isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, unsigned& destReg) const; - unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; - unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; + unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; + unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const; bool isReallyTriviallyReMaterializable(const MachineInstr *MI) const; void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, const MachineInstr *Orig) const; - bool isInvariantLoad(MachineInstr *MI) const; + bool isInvariantLoad(const MachineInstr *MI) const; /// convertToThreeAddress - This method must be implemented by targets that /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index 4d0f42a..8e6a5af 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -75,7 +75,7 @@ bool XCoreInstrInfo::isMoveInstr(const MachineInstr &MI, /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. unsigned -XCoreInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ +XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const{ int Opcode = MI->getOpcode(); if (Opcode == XCore::LDWSP_ru6 || Opcode == XCore::LDWSP_lru6) { @@ -96,7 +96,8 @@ XCoreInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{ /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. unsigned -XCoreInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { +XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const { int Opcode = MI->getOpcode(); if (Opcode == XCore::STWSP_ru6 || Opcode == XCore::STWSP_lru6) { @@ -126,7 +127,7 @@ XCoreInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const { /// only return true of *all* loads the instruction does are invariant (if it /// does multiple loads). bool -XCoreInstrInfo::isInvariantLoad(MachineInstr *MI) const { +XCoreInstrInfo::isInvariantLoad(const MachineInstr *MI) const { // Loads from constants pools and loads from invariant argument slots are // invariant int Opcode = MI->getOpcode(); diff --git a/lib/Target/XCore/XCoreInstrInfo.h b/lib/Target/XCore/XCoreInstrInfo.h index 6213f17..6a246b4 100644 --- a/lib/Target/XCore/XCoreInstrInfo.h +++ b/lib/Target/XCore/XCoreInstrInfo.h @@ -41,16 +41,18 @@ public: /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const; + virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const; /// isStoreToStackSlot - If the specified machine instruction is a direct /// store to a stack slot, return the virtual or physical register number of /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const; + virtual unsigned isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const; - virtual bool isInvariantLoad(MachineInstr *MI) const; + virtual bool isInvariantLoad(const MachineInstr *MI) const; virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, |