Add 8-bit regclass and pattern for sext_inreg

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70721 91177308-0d34-0410-b5e6-96231b3b80d8

4 files changed, 105 insertions, 46 deletions

diff --git a/lib/Target/MSP430/MSP430CallingConv.td b/lib/Target/MSP430/MSP430CallingConv.td
index e60a3de..e582698 100644
--- a/lib/Target/MSP430/MSP430CallingConv.td
+++ b/lib/Target/MSP430/MSP430CallingConv.td
@@ -14,7 +14,7 @@
 //===----------------------------------------------------------------------===//
 def RetCC_MSP430 : CallingConv<[
   // i16 are returned in registers R15, R14, R13, R12
-  CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>
+  CCIfType<[i16], CCAssignToReg<[R15W, R14W, R13W, R12W]>>
 ]>;
 
 //===----------------------------------------------------------------------===//
@@ -26,7 +26,7 @@ def CC_MSP430 : CallingConv<[
 
   // The first 4 integer arguments of non-varargs functions are passed in
   // integer registers.
-  CCIfNotVarArg<CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>>,
+  CCIfNotVarArg<CCIfType<[i16], CCAssignToReg<[R15W, R14W, R13W, R12W]>>>,
 
   // Integer values get stored in stack slots that are 2 bytes in
   // size and 2-byte aligned.
diff --git a/lib/Target/MSP430/MSP430InstrInfo.td b/lib/Target/MSP430/MSP430InstrInfo.td
index d1d02db..d8c0626 100644
--- a/lib/Target/MSP430/MSP430InstrInfo.td
+++ b/lib/Target/MSP430/MSP430InstrInfo.td
@@ -69,89 +69,95 @@ def MOV16ri : Pseudo<(outs GR16:$dst), (ins i16imm:$src),
 
 let isTwoAddress = 1 in {
 
-let Defs = [SR] in {
+let Defs = [SRW] in {
 
 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 // FIXME: Provide proper encoding!
 def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                      "add.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
-                      (implicit SR)]>;
+                      (implicit SRW)]>;
 }
 
 def ADD16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                      "add.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (add GR16:$src1, imm:$src2)),
-                      (implicit SR)]>;
+                      (implicit SRW)]>;
 
-let Uses = [SR] in {
+let Uses = [SRW] in {
 
 let isCommutable = 1 in { // X = ADDC Y, Z  == X = ADDC Z, Y
 def ADC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                      "addc.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (adde GR16:$src1, GR16:$src2)),
-                      (implicit SR)]>;
+                      (implicit SRW)]>;
 } // isCommutable
 
 def ADC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                      "addc.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (adde GR16:$src1, imm:$src2)),
-                      (implicit SR)]>;
+                      (implicit SRW)]>;
 }
 
 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
 def AND16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                      "and.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (and GR16:$src1, GR16:$src2)),
-                      (implicit SR)]>;
+                      (implicit SRW)]>;
 }
 
 def AND16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                      "and.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (and GR16:$src1, imm:$src2)),
-                      (implicit SR)]>;
+                      (implicit SRW)]>;
 
 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 def XOR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                      "xor.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (xor GR16:$src1, GR16:$src2)),
-                      (implicit SR)]>;
+                      (implicit SRW)]>;
 }
 
 def XOR16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                      "xor.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (xor GR16:$src1, imm:$src2)),
-                      (implicit SR)]>;
+                      (implicit SRW)]>;
 
 
 def SUB16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                      "sub.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (sub GR16:$src1, GR16:$src2)),
-                      (implicit SR)]>;
+                      (implicit SRW)]>;
 
 def SUB16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                      "sub.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (sub GR16:$src1, imm:$src2)),
-                      (implicit SR)]>;
+                      (implicit SRW)]>;
 
-let Uses = [SR] in {
+let Uses = [SRW] in {
 def SBC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
                      "subc.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (sube GR16:$src1, GR16:$src2)),
-                      (implicit SR)]>;
+                      (implicit SRW)]>;
 
 def SBC16ri : Pseudo<(outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
                      "subc.w\t{$src2, $dst|$dst, $src2}",
                      [(set GR16:$dst, (sube GR16:$src1, imm:$src2)),
-                      (implicit SR)]>;
+                      (implicit SRW)]>;
 }
 
 // FIXME: Provide proper encoding!
 def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
                      "rra.w\t$dst",
                      [(set GR16:$dst, (MSP430rra GR16:$src)),
-                      (implicit SR)]>;
-} // Defs = [SR]
+                      (implicit SRW)]>;
+
+def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
+                     "sxt\t$dst",
+                     [(set GR16:$dst, (sext_inreg GR16:$src, i8)),
+                      (implicit SRW)]>;
+
+} // Defs = [SRW]
 
 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 def OR16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.cpp b/lib/Target/MSP430/MSP430RegisterInfo.cpp
index ff6d531..292dd28 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.cpp
+++ b/lib/Target/MSP430/MSP430RegisterInfo.cpp
@@ -31,8 +31,8 @@ MSP430RegisterInfo::MSP430RegisterInfo(const TargetInstrInfo &tii)
 const unsigned*
 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   static const unsigned CalleeSavedRegs[] = {
-    MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
-    MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
+    MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
+    MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
     0
   };
 
@@ -57,14 +57,14 @@ MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
 
   // Mark 4 special registers as reserved.
-  Reserved.set(MSP430::PC);
-  Reserved.set(MSP430::SP);
-  Reserved.set(MSP430::SR);
-  Reserved.set(MSP430::CG);
+  Reserved.set(MSP430::PCW);
+  Reserved.set(MSP430::SPW);
+  Reserved.set(MSP430::SRW);
+  Reserved.set(MSP430::CGW);
 
   // Mark frame pointer as reserved if needed.
   if (hasFP(MF))
-    Reserved.set(MSP430::FP);
+    Reserved.set(MSP430::FPW);
 
   return Reserved;
 }
diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td
index cc17e32..7564402 100644
--- a/lib/Target/MSP430/MSP430RegisterInfo.td
+++ b/lib/Target/MSP430/MSP430RegisterInfo.td
@@ -16,37 +16,90 @@ class MSP430Reg<bits<4> num, string n> : Register<n> {
   let Namespace = "MSP430";
 }
 
+class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs> 
+  : RegisterWithSubRegs<n, subregs> {
+  field bits<4> Num = num;
+  let Namespace = "MSP430";
+}
+
 //===----------------------------------------------------------------------===//
 //  Registers
 //===----------------------------------------------------------------------===//
 
-def PC  : MSP430Reg<0,  "r0">;
-def SP  : MSP430Reg<1,  "r1">;
-def SR  : MSP430Reg<2,  "r2">;
-def CG  : MSP430Reg<3,  "r3">;
-def FP  : MSP430Reg<4,  "r4">;
-def R5  : MSP430Reg<5,  "r5">;
-def R6  : MSP430Reg<6,  "r6">;
-def R7  : MSP430Reg<7,  "r7">;
-def R8  : MSP430Reg<8,  "r8">;
-def R9  : MSP430Reg<9,  "r9">;
-def R10 : MSP430Reg<10, "r10">;
-def R11 : MSP430Reg<11, "r11">;
-def R12 : MSP430Reg<12, "r12">;
-def R13 : MSP430Reg<13, "r13">;
-def R14 : MSP430Reg<14, "r14">;
-def R15 : MSP430Reg<15, "r15">;
+def PCB  : MSP430Reg<0,  "r0">;
+def SPB  : MSP430Reg<1,  "r1">;
+def SRB  : MSP430Reg<2,  "r2">;
+def CGB  : MSP430Reg<3,  "r3">;
+def FPB  : MSP430Reg<4,  "r4">;
+def R5B  : MSP430Reg<5,  "r5">;
+def R6B  : MSP430Reg<6,  "r6">;
+def R7B  : MSP430Reg<7,  "r7">;
+def R8B  : MSP430Reg<8,  "r8">;
+def R9B  : MSP430Reg<9,  "r9">;
+def R10B : MSP430Reg<10, "r10">;
+def R11B : MSP430Reg<11, "r11">;
+def R12B : MSP430Reg<12, "r12">;
+def R13B : MSP430Reg<13, "r13">;
+def R14B : MSP430Reg<14, "r14">;
+def R15B : MSP430Reg<15, "r15">;
 
-// FIXME: we need subregs & special handling for 8 bit stuff
+def PCW  : MSP430RegWithSubregs<0,  "r0",  [PCB]>;
+def SPW  : MSP430RegWithSubregs<1,  "r1",  [SPB]>;
+def SRW  : MSP430RegWithSubregs<2,  "r2",  [SRB]>;
+def CGW  : MSP430RegWithSubregs<3,  "r3",  [CGB]>;
+def FPW  : MSP430RegWithSubregs<4,  "r4",  [FPB]>;
+def R5W  : MSP430RegWithSubregs<5,  "r5",  [R5B]>;
+def R6W  : MSP430RegWithSubregs<6,  "r6",  [R6B]>;
+def R7W  : MSP430RegWithSubregs<7,  "r7",  [R7B]>;
+def R8W  : MSP430RegWithSubregs<8,  "r8",  [R8B]>;
+def R9W  : MSP430RegWithSubregs<9,  "r9",  [R9B]>;
+def R10W : MSP430RegWithSubregs<10, "r10", [R10B]>;
+def R11W : MSP430RegWithSubregs<11, "r11", [R11B]>;
+def R12W : MSP430RegWithSubregs<12, "r12", [R12B]>;
+def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>;
+def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>;
+def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>;
+
+def : SubRegSet<1, [PCW, SPW, SRW, CGW, FPW,
+                    R5W, R6W, R7W, R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W],
+                   [PCB, SPB, SRB, CGB, FPB,
+                    R5B, R6B, R7B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B]>;
+
+def GR8 : RegisterClass<"MSP430", [i8], 8,
+   // Volatile registers
+  [R12B, R13B, R14B, R15B, R11B, R10B, R9B, R8B, R7B, R6B, R5B,
+   // Frame pointer, sometimes allocable
+   FPB,
+   // Volatile, but not allocable
+   PCB, SPB, SRB, CGB]>
+{
+  let MethodProtos = [{
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  let MethodBodies = [{
+    GR8Class::iterator
+    GR8Class::allocation_order_end(const MachineFunction &MF) const {
+      const TargetMachine &TM = MF.getTarget();
+      const TargetRegisterInfo *RI = TM.getRegisterInfo();
+      // Depending on whether the function uses frame pointer or not, last 5 or 4
+      // registers on the list above are reserved
+      if (RI->hasFP(MF))
+        return end()-5;
+      else
+        return end()-4;
+    }
+  }];
+}
 
 def GR16 : RegisterClass<"MSP430", [i16], 16,
    // Volatile registers
-  [R12, R13, R14, R15, R11, R10, R9, R8, R7, R6, R5,
+  [R12W, R13W, R14W, R15W, R11W, R10W, R9W, R8W, R7W, R6W, R5W,
    // Frame pointer, sometimes allocable
-   FP,
+   FPW,
    // Volatile, but not allocable
-   PC, SP, SR, CG]>
+   PCW, SPW, SRW, CGW]>
 {
+  let SubRegClassList = [GR8];
   let MethodProtos = [{
     iterator allocation_order_end(const MachineFunction &MF) const;
   }];