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| author | Tim Northover <tnorthover@apple.com> | 2013-07-01 14:48:48 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-07-01 14:48:48 +0000 |
| commit | d59fc0af0a3ebd13c7004511e64e3233dfe87b17 (patch) | |
| tree | 1cc4dbfa52c9735cb04654858ebc786c87a15509 /lib/Target | |
| parent | 728af3d574895dd9e4bb5c418c7398297c4f39fe (diff) | |
| download | external_llvm-d59fc0af0a3ebd13c7004511e64e3233dfe87b17.zip external_llvm-d59fc0af0a3ebd13c7004511e64e3233dfe87b17.tar.gz external_llvm-d59fc0af0a3ebd13c7004511e64e3233dfe87b17.tar.bz2 | |
ARM: relax the atomic release barrier to "dmb ishst"
I believe the full "dmb ish" barrier is not required to guarantee release
semantics for atomic operations. The weaker "dmb ishst" prevents previous
operations being reordered with a store executed afterwards, which is enough.
A key point to note (fortunately already correct) is that this barrier alone is
*insufficient* for sequential consistency, no matter how liberally placed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185339 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index ff8571b..370962d 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -2557,8 +2557,12 @@ static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, DAG.getConstant(0, MVT::i32)); } + ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1)); + AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue()); + unsigned Domain = Ord == Release ? ARM_MB::ISHST : ARM_MB::ISH; + return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), - DAG.getConstant(ARM_MB::ISH, MVT::i32)); + DAG.getConstant(Domain, MVT::i32)); } static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, |