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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:20:53 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2010-04-07 18:20:53 +0000 |
| commit | d76da03e91e5ae31e944bd5e8f0c4a93bc6984e5 (patch) | |
| tree | 9e3d2f2903e5778733e9d6557aa6672e98e437c0 /lib/Target | |
| parent | dc0bab70cfc0fe2f80e0b4c310581f4cfa57bfe4 (diff) | |
| download | external_llvm-d76da03e91e5ae31e944bd5e8f0c4a93bc6984e5.zip external_llvm-d76da03e91e5ae31e944bd5e8f0c4a93bc6984e5.tar.gz external_llvm-d76da03e91e5ae31e944bd5e8f0c4a93bc6984e5.tar.bz2 | |
Fix invalid NEON MAC itins on A8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100659 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMScheduleV7.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/ARM/ARMScheduleV7.td b/lib/Target/ARM/ARMScheduleV7.td index 03b0ce8..7bd8811 100644 --- a/lib/Target/ARM/ARMScheduleV7.td +++ b/lib/Target/ARM/ARMScheduleV7.td @@ -551,21 +551,21 @@ def CortexA8Itineraries : ProcessorItineraries<[ // // Double-register Integer Multiply-Accumulate (.8, .16) InstrItinData<IIC_VMACi16D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, - InstrStage<1, [FU_NPipe]>], [6, 2, 2, 3]>, + InstrStage<1, [FU_NPipe]>], [6, 3, 2, 2]>, // // Double-register Integer Multiply-Accumulate (.32) InstrItinData<IIC_VMACi32D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, - InstrStage<2, [FU_NPipe]>], [7, 2, 1, 3]>, + InstrStage<2, [FU_NPipe]>], [7, 3, 2, 1]>, // // Quad-register Integer Multiply-Accumulate (.8, .16) InstrItinData<IIC_VMACi16Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, - InstrStage<2, [FU_NPipe]>], [7, 2, 2, 3]>, + InstrStage<2, [FU_NPipe]>], [7, 3, 2, 2]>, // // Quad-register Integer Multiply-Accumulate (.32) InstrItinData<IIC_VMACi32Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, InstrStage<1, [FU_NPipe]>, InstrStage<2, [FU_NLSPipe], 0>, - InstrStage<3, [FU_NPipe]>], [9, 2, 1, 3]>, + InstrStage<3, [FU_NPipe]>], [9, 3, 2, 1]>, // // Double-register VEXT InstrItinData<IIC_VEXTD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>, |