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| author | Dan Gohman <gohman@apple.com> | 2008-08-08 18:30:21 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-08-08 18:30:21 +0000 |
| commit | d9ced092998b5ea3b10ab32b8f2407022b4508db (patch) | |
| tree | 2897c82940e2fe6efa8734af214d0a5ce4989177 /lib/Target | |
| parent | cbdf30af797115fed613cec7739c4ae0cd52abb1 (diff) | |
| download | external_llvm-d9ced092998b5ea3b10ab32b8f2407022b4508db.zip external_llvm-d9ced092998b5ea3b10ab32b8f2407022b4508db.tar.gz external_llvm-d9ced092998b5ea3b10ab32b8f2407022b4508db.tar.bz2 | |
Add an EXTRACTPSmr pattern to match the pattern that
X86ISelLowering creates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54544 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index a871fa8..d800c97 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -238,6 +238,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) { X86::DIV32r, X86::DIV32m, 1 }, { X86::DIV64r, X86::DIV64m, 1 }, { X86::DIV8r, X86::DIV8m, 1 }, + { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0 }, { X86::FsMOVAPDrr, X86::MOVSDmr, 0 }, { X86::FsMOVAPSrr, X86::MOVSSmr, 0 }, { X86::IDIV16r, X86::IDIV16m, 1 }, diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 856525e..963a605 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -3485,6 +3485,13 @@ multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> { defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">; +// Also match an EXTRACTPS store when the store is done as f32 instead of i32. +def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)), + imm:$src2))), + addr:$dst), + (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>, + Requires<[HasSSE41]>; + let Constraints = "$src1 = $dst" in { multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> { def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst), |