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author | Evan Cheng <evan.cheng@apple.com> | 2009-06-23 18:14:38 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-06-23 18:14:38 +0000 |
commit | e499f970585c2462e2de8a38f67f6d11683a6bb0 (patch) | |
tree | 122a06d2905314babf1965a982aede8a29fc5550 /lib/Target | |
parent | cd92c1000eeceb195daaab47ca4a2161ab2da410 (diff) | |
download | external_llvm-e499f970585c2462e2de8a38f67f6d11683a6bb0.zip external_llvm-e499f970585c2462e2de8a38f67f6d11683a6bb0.tar.gz external_llvm-e499f970585c2462e2de8a38f67f6d11683a6bb0.tar.bz2 |
Rename SelectShifterOperand to SelectThumb2ShifterOperandReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73975 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMISelDAGToDAG.cpp | 12 | ||||
-rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 2 |
2 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index ee9dadf..be543a9 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -92,8 +92,8 @@ public: bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base, SDValue &OffImm); - bool SelectShifterOperand(SDValue Op, SDValue N, - SDValue &BaseReg, SDValue &Opc); + bool SelectThumb2ShifterOperandReg(SDValue Op, SDValue N, + SDValue &BaseReg, SDValue &Opc); bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A, SDValue &B, SDValue &C); @@ -520,10 +520,10 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N, return false; } -bool ARMDAGToDAGISel::SelectShifterOperand(SDValue Op, - SDValue N, - SDValue &BaseReg, - SDValue &Opc) { +bool ARMDAGToDAGISel::SelectThumb2ShifterOperandReg(SDValue Op, + SDValue N, + SDValue &BaseReg, + SDValue &Opc) { ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N); // Don't match base register only case. That is matched to a separate diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 9790c2b..e0617e4 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -14,7 +14,7 @@ // Shifted operands. No register controlled shifts for Thumb2. // Note: We do not support rrx shifted operands yet. def t2_so_reg : Operand<i32>, // reg imm - ComplexPattern<i32, 2, "SelectShifterOperand", + ComplexPattern<i32, 2, "SelectThumb2ShifterOperandReg", [shl,srl,sra,rotr]> { let PrintMethod = "printSOOperand"; let MIOperandInfo = (ops GPR, i32imm); |