Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6320 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 71 insertions, 1 deletions

diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
index d914a6c..0ad163c 100644
--- a/lib/Target/SparcV9/SparcV9Internals.h
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -8,6 +8,7 @@
 #ifndef SPARC_INTERNALS_H
 #define SPARC_INTERNALS_H
 
+#include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetSchedInfo.h"
 #include "llvm/Target/TargetFrameInfo.h"
@@ -15,6 +16,7 @@
 #include "llvm/Target/TargetRegInfo.h"
 #include "llvm/Target/TargetOptInfo.h"
 #include "llvm/Type.h"
+#include "SparcRegClassInfo.h"
 #include <sys/types.h>
 
 class LiveRange;
@@ -102,6 +104,33 @@ struct UltraSparcInstrInfo : public TargetInstrInfo {
     else
       return -1;
   }
+
+  /// createNOPinstr - returns the target's implementation of NOP, which is
+  /// usually a pseudo-instruction, implemented by a degenerate version of
+  /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi g0, 0
+  ///
+  MachineInstr* createNOPinstr() const {
+    return BuildMI(V9::SETHI, 2).addReg(SparcIntRegClass::g0).addZImm(0);
+  }
+
+  /// isNOPinstr - since we no longer have a special NOP opcode, we need to know
+  /// if a given instruction is interpreted as an `official' NOP instr, i.e.,
+  /// there may be more than one way to `do nothing' but only one canonical
+  /// way to slack off.
+  ///
+  bool isNOPinstr(const MachineInstr &MI) const {
+    // Make sure the instruction is EXACTLY `sethi g0, 0'
+    if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
+      const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
+      if (op0.isMachineRegister() &&
+          op0.getMachineRegNum() == SparcIntRegClass::g0 &&
+          op1.isImmediate() && op1.getImmedValue() == 0)
+      {
+        return true;
+      }
+    }
+    return false;
+  }
   
   virtual bool hasResultInterlock(MachineOpCode opCode) const
   {
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 6b2fd64..182798e 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -6,7 +6,7 @@
 
 #include "X86InstrInfo.h"
 #include "X86.h"
-#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
 
 #define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES)
 #define IMPREGSLIST(NAME, ...) \
@@ -39,6 +39,34 @@ X86InstrInfo::X86InstrInfo()
 }
 
 
+// createNOPinstr - returns the target's implementation of NOP, which is
+// usually a pseudo-instruction, implemented by a degenerate version of
+// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
+//
+MachineInstr* X86InstrInfo::createNOPinstr() const {
+  return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX).addReg(X86::AX);
+}
+
+
+// isNOPinstr - since we no longer have a special NOP opcode, we need to know
+// if a given instruction is interpreted as an `official' NOP instr, i.e.,
+// there may be more than one way to `do nothing' but only one canonical
+// way to slack off.
+//
+bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
+  // Make sure the instruction is EXACTLY `xchg ax, ax'
+  if (MI.getOpcode() == X86::XCHGrr16 && MI.getNumOperands() == 2) {
+    const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
+    if (op0.isMachineRegister() && op0.getMachineRegNum() == X86::AX &&
+        op1.isMachineRegister() && op1.getMachineRegNum() == X86::AX)
+    {
+      return true;
+    }
+  }
+  return false;
+}
+
+
 static unsigned char BaseOpcodes[] = {
 #define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) BASEOPCODE,
 #include "X86InstrInfo.def"
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index 593fc0e..8dacf97 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -148,6 +148,19 @@ public:
   ///
   virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
 
+  /// createNOPinstr - returns the target's implementation of NOP, which is
+  /// usually a pseudo-instruction, implemented by a degenerate version of
+  /// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
+  ///
+  MachineInstr* createNOPinstr() const;
+
+  /// isNOPinstr - since we no longer have a special NOP opcode, we need to know
+  /// if a given instruction is interpreted as an `official' NOP instr, i.e.,
+  /// there may be more than one way to `do nothing' but only one canonical
+  /// way to slack off.
+  ///
+  bool isNOPinstr(const MachineInstr &MI) const;
+
   /// print - Print out an x86 instruction in intel syntax
   ///
   virtual void print(const MachineInstr *MI, std::ostream &O,