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author | Eric Christopher <echristo@apple.com> | 2010-10-07 05:50:44 +0000 |
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committer | Eric Christopher <echristo@apple.com> | 2010-10-07 05:50:44 +0000 |
commit | ee56ea62431081a2333eb47df3fa4dfcd425cb54 (patch) | |
tree | d7e144a5992a5c83043d01d55b6f6cbeea930143 /lib/Target | |
parent | 5d18d92aad587381b5d9ecf0aeb3c2eb1530ee61 (diff) | |
download | external_llvm-ee56ea62431081a2333eb47df3fa4dfcd425cb54.zip external_llvm-ee56ea62431081a2333eb47df3fa4dfcd425cb54.tar.gz external_llvm-ee56ea62431081a2333eb47df3fa4dfcd425cb54.tar.bz2 |
Use the correct register class for load instructions - fixes
compilation of MultiSource/Benchmarks/Bullet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115907 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 9e8e1df..497259c 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -652,33 +652,40 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, assert(VT.isSimple() && "Non-simple types are invalid here!"); unsigned Opc; + TargetRegisterClass *RC; bool isFloat = false; switch (VT.getSimpleVT().SimpleTy) { default: // This is mostly going to be Neon/vector support. return false; + // Using thumb1 instructions for now, use the appropriate RC. case MVT::i16: Opc = isThumb ? ARM::tLDRH : ARM::LDRH; + RC = isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; VT = MVT::i32; break; case MVT::i8: Opc = isThumb ? ARM::tLDRB : ARM::LDRB; + RC = isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; VT = MVT::i32; break; case MVT::i32: Opc = isThumb ? ARM::tLDR : ARM::LDR; + RC = isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; break; case MVT::f32: Opc = ARM::VLDRS; + RC = TLI.getRegClassFor(VT); isFloat = true; break; case MVT::f64: Opc = ARM::VLDRD; + RC = TLI.getRegClassFor(VT); isFloat = true; break; } - ResultReg = createResultReg(TLI.getRegClassFor(VT)); + ResultReg = createResultReg(RC); // TODO: Fix the Addressing modes so that these can share some code. // Since this is a Thumb1 load this will work in Thumb1 or 2 mode. |