Enable the new no-SP register classes by default. This is to address

PR4572. A few tests have some minor code regressions due to different
coalescing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78217 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 6 insertions, 17 deletions

diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index 94bb1de..a76a056 100644
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -32,13 +32,13 @@ def i64i8imm   : Operand<i64>;
 
 def lea64mem : Operand<i64> {
   let PrintMethod = "printlea64mem";
-  let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
+  let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm);
 }
 
 def lea64_32mem : Operand<i32> {
   let PrintMethod = "printlea64_32mem";
   let AsmOperandLowerMethod = "lower_lea64_32mem";
-  let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
+  let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
 }
 
 //===----------------------------------------------------------------------===//
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index bbf0cb5..65b1e9d 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -196,7 +196,7 @@ def i8mem_NOREX : Operand<i64> {
 
 def lea32mem : Operand<i32> {
   let PrintMethod = "printlea32mem";
-  let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
+  let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm);
 }
 
 def SSECC : Operand<i8> {
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 21f4dc5..cae6290 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -42,11 +42,6 @@
 #include "llvm/Support/ErrorHandling.h"
 using namespace llvm;
 
-static cl::opt<bool>
-StrictIndexRegclass("strict-index-regclass",
-                    cl::desc("Use a special register class to avoid letting SP "
-                             "be used as an index"));
-
 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
                                  const TargetInstrInfo &tii)
   : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
@@ -274,15 +269,9 @@ getPointerRegClass(unsigned Kind) const {
       return &X86::GR64RegClass;
     return &X86::GR32RegClass;
   case 1: // Normal GRPs except the stack pointer (for encoding reasons).
-    if (!StrictIndexRegclass) {
-      if (TM.getSubtarget<X86Subtarget>().is64Bit())
-        return &X86::GR64RegClass;
-      return &X86::GR32RegClass;
-    } else {
-      if (TM.getSubtarget<X86Subtarget>().is64Bit())
-        return &X86::GR64_NOSPRegClass;
-      return &X86::GR32_NOSPRegClass;
-    }
+    if (TM.getSubtarget<X86Subtarget>().is64Bit())
+      return &X86::GR64_NOSPRegClass;
+    return &X86::GR32_NOSPRegClass;
   }
 }