[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189467 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 327 insertions, 14 deletions

diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td
index 8383646..e7688ca 100644
--- a/lib/Target/Mips/MipsMSAInstrInfo.td
+++ b/lib/Target/Mips/MipsMSAInstrInfo.td
@@ -258,6 +258,9 @@ class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
 class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
 class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
 
+class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
+class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
+
 class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
 class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
 
@@ -270,12 +273,27 @@ class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
 
-class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
-class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
+class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
+class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
+
+class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
+class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
+
+class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
+class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
+
+class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
+class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
+
+class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
+class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
 
 class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
 class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
 
+class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
+class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
+
 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
 
@@ -340,6 +358,9 @@ class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
 class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
 class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
 
+class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
+class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
+
 class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
 class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
 
@@ -349,8 +370,11 @@ class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
 class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
 class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
 
-class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
-class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
+class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
+class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
+
+class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
+class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
 
 class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
 class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
@@ -358,6 +382,27 @@ class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
 class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
 class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
 
+class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
+class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
+
+class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
+class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
+
+class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
+class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
+
+class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
+class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
+
+class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
+class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
+
+class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110100000, 0b0, 0b011110>;
+class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110100000, 0b1, 0b011110>;
+
+class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110100001, 0b0, 0b011110>;
+class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110100001, 0b1, 0b011110>;
+
 class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
 class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
 
@@ -367,6 +412,22 @@ class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
 class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
 class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
 
+class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
+class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
+class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
+
+class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
+class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
+class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
+
+class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
+class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
+class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
+
+class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
+class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
+class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
+
 class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
 class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
 class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
@@ -406,11 +467,11 @@ class LDI_H_ENC   : MSA_I10_FMT<0b010, 0b01, 0b001100>;
 class LDI_W_ENC   : MSA_I10_FMT<0b010, 0b10, 0b001100>;
 class LDI_D_ENC   : MSA_I10_FMT<0b010, 0b11, 0b001100>;
 
-class MADD_Q_H_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
-class MADD_Q_W_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
+class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
+class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
 
-class MADDR_Q_H_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
-class MADDR_Q_W_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
+class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
+class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
 
 class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
 class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
@@ -477,11 +538,11 @@ class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
 class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
 class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
 
-class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
-class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
+class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
+class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
 
-class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
-class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
+class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
+class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
 
 class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
 class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
@@ -491,8 +552,8 @@ class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011100>;
 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011100>;
 
-class MULR_Q_H_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
-class MULR_Q_W_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
+class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
+class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
 
 class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
 class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
@@ -586,6 +647,16 @@ class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
 class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
 class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
 
+class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
+class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
+class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
+class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
+
+class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
+class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
+class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
+class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
+
 class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
 class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
 class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
@@ -596,6 +667,16 @@ class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
 class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
 class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
 
+class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
+class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
+class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
+class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
+
+class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
+class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
+class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
+class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
+
 class ST_B_ENC   : MSA_I5_FMT<0b111, 0b00, 0b000111>;
 class ST_H_ENC   : MSA_I5_FMT<0b111, 0b01, 0b000111>;
 class ST_W_ENC   : MSA_I5_FMT<0b111, 0b10, 0b000111>;
@@ -1245,6 +1326,13 @@ class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", int_mips_fadd_d,
                                       NoItinerary, MSA128D, MSA128D>,
                                       IsCommutable;
 
+class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w,
+                                      NoItinerary, MSA128W, MSA128W>,
+                                      IsCommutable;
+class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d,
+                                      NoItinerary, MSA128D, MSA128D>,
+                                      IsCommutable;
+
 class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", int_mips_fceq_w,
                                       NoItinerary, MSA128W, MSA128W>,
                                       IsCommutable;
@@ -1274,6 +1362,34 @@ class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", int_mips_fcne_d,
                                       NoItinerary, MSA128D, MSA128D>,
                                       IsCommutable;
 
+class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", int_mips_fcor_w,
+                                      NoItinerary, MSA128W, MSA128W>,
+                                      IsCommutable;
+class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", int_mips_fcor_d,
+                                      NoItinerary, MSA128D, MSA128D>,
+                                      IsCommutable;
+
+class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", int_mips_fcueq_w,
+                                       NoItinerary, MSA128W, MSA128W>,
+                                       IsCommutable;
+class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", int_mips_fcueq_d,
+                                       NoItinerary, MSA128D, MSA128D>,
+                                       IsCommutable;
+
+class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", int_mips_fcule_w,
+                                       NoItinerary, MSA128W, MSA128W>,
+                                       IsCommutable;
+class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", int_mips_fcule_d,
+                                       NoItinerary, MSA128D, MSA128D>,
+                                       IsCommutable;
+
+class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", int_mips_fcult_w,
+                                       NoItinerary, MSA128W, MSA128W>,
+                                       IsCommutable;
+class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", int_mips_fcult_d,
+                                       NoItinerary, MSA128D, MSA128D>,
+                                       IsCommutable;
+
 class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", int_mips_fcun_w,
                                       NoItinerary, MSA128W, MSA128W>,
                                       IsCommutable;
@@ -1281,6 +1397,13 @@ class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", int_mips_fcun_d,
                                       NoItinerary, MSA128D, MSA128D>,
                                       IsCommutable;
 
+class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", int_mips_fcune_w,
+                                       NoItinerary, MSA128W, MSA128W>,
+                                       IsCommutable;
+class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", int_mips_fcune_d,
+                                       NoItinerary, MSA128D, MSA128D>,
+                                       IsCommutable;
+
 class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", int_mips_fdiv_w,
                                       NoItinerary, MSA128W, MSA128W>;
 class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", int_mips_fdiv_d,
@@ -1388,6 +1511,11 @@ class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
 class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
                                         NoItinerary, MSA128D, MSA128D>;
 
+class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w,
+                                      NoItinerary, MSA128W, MSA128W>;
+class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d,
+                                      NoItinerary, MSA128D, MSA128D>;
+
 class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w,
                                       NoItinerary, MSA128W, MSA128W>;
 class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d,
@@ -1408,6 +1536,11 @@ class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w,
 class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d,
                                       NoItinerary, MSA128D, MSA128D>;
 
+class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w,
+                                      NoItinerary, MSA128W, MSA128W>;
+class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d,
+                                      NoItinerary, MSA128D, MSA128D>;
+
 class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", int_mips_fsqrt_w,
                                        NoItinerary, MSA128W, MSA128W>;
 class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", int_mips_fsqrt_d,
@@ -1418,6 +1551,41 @@ class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", int_mips_fsub_w,
 class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", int_mips_fsub_d,
                                       NoItinerary, MSA128D, MSA128D>;
 
+class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
+                                       NoItinerary, MSA128W, MSA128W>;
+class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
+                                       NoItinerary, MSA128D, MSA128D>;
+
+class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
+                                       NoItinerary, MSA128W, MSA128W>;
+class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
+                                       NoItinerary, MSA128D, MSA128D>;
+
+class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
+                                       NoItinerary, MSA128W, MSA128W>;
+class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
+                                       NoItinerary, MSA128D, MSA128D>;
+
+class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
+                                      NoItinerary, MSA128W, MSA128W>;
+class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
+                                      NoItinerary, MSA128D, MSA128D>;
+
+class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
+                                       NoItinerary, MSA128W, MSA128W>;
+class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
+                                       NoItinerary, MSA128D, MSA128D>;
+
+class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", int_mips_ftrunc_s_w,
+                                          NoItinerary, MSA128W, MSA128W>;
+class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", int_mips_ftrunc_s_d,
+                                          NoItinerary, MSA128D, MSA128D>;
+
+class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", int_mips_ftrunc_u_w,
+                                          NoItinerary, MSA128W, MSA128W>;
+class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", int_mips_ftrunc_u_d,
+                                          NoItinerary, MSA128D, MSA128D>;
+
 class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
                                          NoItinerary, MSA128W, MSA128W>;
 class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
@@ -1433,6 +1601,34 @@ class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
 class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
                                      NoItinerary, MSA128W, MSA128D>;
 
+class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
+                                       NoItinerary, MSA128H, MSA128B>;
+class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
+                                       NoItinerary, MSA128W, MSA128H>;
+class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
+                                       NoItinerary, MSA128D, MSA128W>;
+
+class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
+                                       NoItinerary, MSA128H, MSA128B>;
+class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
+                                       NoItinerary, MSA128W, MSA128H>;
+class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
+                                       NoItinerary, MSA128D, MSA128W>;
+
+class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
+                                       NoItinerary, MSA128H, MSA128B>;
+class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
+                                       NoItinerary, MSA128W, MSA128H>;
+class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
+                                       NoItinerary, MSA128D, MSA128W>;
+
+class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
+                                       NoItinerary, MSA128H, MSA128B>;
+class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
+                                       NoItinerary, MSA128W, MSA128H>;
+class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
+                                       NoItinerary, MSA128D, MSA128W>;
+
 class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", int_mips_ilvev_b, NoItinerary,
                                       MSA128B, MSA128B>;
 class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", int_mips_ilvev_h, NoItinerary,
@@ -1828,6 +2024,24 @@ class SRAI_W_DESC : MSA_BIT_W_DESC_BASE<"srai.w", int_mips_srai_w,
 class SRAI_D_DESC : MSA_BIT_D_DESC_BASE<"srai.d", int_mips_srai_d,
                                         NoItinerary, MSA128D, MSA128D>;
 
+class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, NoItinerary,
+                                     MSA128B, MSA128B>;
+class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, NoItinerary,
+                                     MSA128H, MSA128H>;
+class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, NoItinerary,
+                                     MSA128W, MSA128W>;
+class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, NoItinerary,
+                                     MSA128D, MSA128D>;
+
+class SRARI_B_DESC : MSA_BIT_B_DESC_BASE<"srari.b", int_mips_srari_b,
+                                         NoItinerary, MSA128B, MSA128B>;
+class SRARI_H_DESC : MSA_BIT_H_DESC_BASE<"srari.h", int_mips_srari_h,
+                                         NoItinerary, MSA128H, MSA128H>;
+class SRARI_W_DESC : MSA_BIT_W_DESC_BASE<"srari.w", int_mips_srari_w,
+                                         NoItinerary, MSA128W, MSA128W>;
+class SRARI_D_DESC : MSA_BIT_D_DESC_BASE<"srari.d", int_mips_srari_d,
+                                         NoItinerary, MSA128D, MSA128D>;
+
 class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", int_mips_srl_b, NoItinerary,
                                     MSA128B, MSA128B>;
 class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", int_mips_srl_h, NoItinerary,
@@ -1846,6 +2060,24 @@ class SRLI_W_DESC : MSA_BIT_W_DESC_BASE<"srli.w", int_mips_srli_w,
 class SRLI_D_DESC : MSA_BIT_D_DESC_BASE<"srli.d", int_mips_srli_d,
                                         NoItinerary, MSA128D, MSA128D>;
 
+class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, NoItinerary,
+                                     MSA128B, MSA128B>;
+class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, NoItinerary,
+                                     MSA128H, MSA128H>;
+class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, NoItinerary,
+                                     MSA128W, MSA128W>;
+class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, NoItinerary,
+                                     MSA128D, MSA128D>;
+
+class SRLRI_B_DESC : MSA_BIT_B_DESC_BASE<"srlri.b", int_mips_srlri_b,
+                                         NoItinerary, MSA128B, MSA128B>;
+class SRLRI_H_DESC : MSA_BIT_H_DESC_BASE<"srlri.h", int_mips_srlri_h,
+                                         NoItinerary, MSA128H, MSA128H>;
+class SRLRI_W_DESC : MSA_BIT_W_DESC_BASE<"srlri.w", int_mips_srlri_w,
+                                         NoItinerary, MSA128W, MSA128W>;
+class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE<"srlri.d", int_mips_srlri_d,
+                                         NoItinerary, MSA128D, MSA128D>;
+
 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
                    ValueType TyNode, InstrItinClass itin, RegisterClass RCWD,
                    Operand MemOpnd = mem, ComplexPattern Addr = addr> {
@@ -2154,6 +2386,9 @@ def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC, Requires<[HasMSA]>;
 def FADD_W : FADD_W_ENC, FADD_W_DESC, Requires<[HasMSA]>;
 def FADD_D : FADD_D_ENC, FADD_D_DESC, Requires<[HasMSA]>;
 
+def FCAF_W : FCAF_W_ENC, FCAF_W_DESC, Requires<[HasMSA]>;
+def FCAF_D : FCAF_D_ENC, FCAF_D_DESC, Requires<[HasMSA]>;
+
 def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC, Requires<[HasMSA]>;
 def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC, Requires<[HasMSA]>;
 
@@ -2169,9 +2404,24 @@ def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC, Requires<[HasMSA]>;
 def FCNE_W : FCNE_W_ENC, FCNE_W_DESC, Requires<[HasMSA]>;
 def FCNE_D : FCNE_D_ENC, FCNE_D_DESC, Requires<[HasMSA]>;
 
+def FCOR_W : FCOR_W_ENC, FCOR_W_DESC, Requires<[HasMSA]>;
+def FCOR_D : FCOR_D_ENC, FCOR_D_DESC, Requires<[HasMSA]>;
+
+def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC, Requires<[HasMSA]>;
+def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC, Requires<[HasMSA]>;
+
+def FCULE_W : FCULE_W_ENC, FCULE_W_DESC, Requires<[HasMSA]>;
+def FCULE_D : FCULE_D_ENC, FCULE_D_DESC, Requires<[HasMSA]>;
+
+def FCULT_W : FCULT_W_ENC, FCULT_W_DESC, Requires<[HasMSA]>;
+def FCULT_D : FCULT_D_ENC, FCULT_D_DESC, Requires<[HasMSA]>;
+
 def FCUN_W : FCUN_W_ENC, FCUN_W_DESC, Requires<[HasMSA]>;
 def FCUN_D : FCUN_D_ENC, FCUN_D_DESC, Requires<[HasMSA]>;
 
+def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC, Requires<[HasMSA]>;
+def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC, Requires<[HasMSA]>;
+
 def FDIV_W : FDIV_W_ENC, FDIV_W_DESC, Requires<[HasMSA]>;
 def FDIV_D : FDIV_D_ENC, FDIV_D_DESC, Requires<[HasMSA]>;
 
@@ -2236,6 +2486,9 @@ def FRCP_D : FRCP_D_ENC, FRCP_D_DESC, Requires<[HasMSA]>;
 def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC, Requires<[HasMSA]>;
 def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC, Requires<[HasMSA]>;
 
+def FSAF_W : FSAF_W_ENC, FSAF_W_DESC, Requires<[HasMSA]>;
+def FSAF_D : FSAF_D_ENC, FSAF_D_DESC, Requires<[HasMSA]>;
+
 def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC, Requires<[HasMSA]>;
 def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC, Requires<[HasMSA]>;
 
@@ -2248,12 +2501,36 @@ def FSLT_D : FSLT_D_ENC, FSLT_D_DESC, Requires<[HasMSA]>;
 def FSNE_W : FSNE_W_ENC, FSNE_W_DESC, Requires<[HasMSA]>;
 def FSNE_D : FSNE_D_ENC, FSNE_D_DESC, Requires<[HasMSA]>;
 
+def FSOR_W : FSOR_W_ENC, FSOR_W_DESC, Requires<[HasMSA]>;
+def FSOR_D : FSOR_D_ENC, FSOR_D_DESC, Requires<[HasMSA]>;
+
 def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC, Requires<[HasMSA]>;
 def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC, Requires<[HasMSA]>;
 
 def FSUB_W : FSUB_W_ENC, FSUB_W_DESC, Requires<[HasMSA]>;
 def FSUB_D : FSUB_D_ENC, FSUB_D_DESC, Requires<[HasMSA]>;
 
+def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC, Requires<[HasMSA]>;
+def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC, Requires<[HasMSA]>;
+
+def FSULE_W : FSULE_W_ENC, FSULE_W_DESC, Requires<[HasMSA]>;
+def FSULE_D : FSULE_D_ENC, FSULE_D_DESC, Requires<[HasMSA]>;
+
+def FSULT_W : FSULT_W_ENC, FSULT_W_DESC, Requires<[HasMSA]>;
+def FSULT_D : FSULT_D_ENC, FSULT_D_DESC, Requires<[HasMSA]>;
+
+def FSUN_W : FSUN_W_ENC, FSUN_W_DESC, Requires<[HasMSA]>;
+def FSUN_D : FSUN_D_ENC, FSUN_D_DESC, Requires<[HasMSA]>;
+
+def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC, Requires<[HasMSA]>;
+def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC, Requires<[HasMSA]>;
+
+def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC, Requires<[HasMSA]>;
+def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC, Requires<[HasMSA]>;
+
+def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC, Requires<[HasMSA]>;
+def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC, Requires<[HasMSA]>;
+
 def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC, Requires<[HasMSA]>;
 def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC, Requires<[HasMSA]>;
 
@@ -2263,6 +2540,22 @@ def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC, Requires<[HasMSA]>;
 def FTQ_H : FTQ_H_ENC, FTQ_H_DESC, Requires<[HasMSA]>;
 def FTQ_W : FTQ_W_ENC, FTQ_W_DESC, Requires<[HasMSA]>;
 
+def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC, Requires<[HasMSA]>;
+def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC, Requires<[HasMSA]>;
+def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC, Requires<[HasMSA]>;
+
+def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC, Requires<[HasMSA]>;
+def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC, Requires<[HasMSA]>;
+def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC, Requires<[HasMSA]>;
+
+def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC, Requires<[HasMSA]>;
+def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC, Requires<[HasMSA]>;
+def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC, Requires<[HasMSA]>;
+
+def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC, Requires<[HasMSA]>;
+def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC, Requires<[HasMSA]>;
+def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC, Requires<[HasMSA]>;
+
 def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC, Requires<[HasMSA]>;
 def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC, Requires<[HasMSA]>;
 def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC, Requires<[HasMSA]>;
@@ -2481,6 +2774,16 @@ def SRAI_H : SRAI_H_ENC, SRAI_H_DESC, Requires<[HasMSA]>;
 def SRAI_W : SRAI_W_ENC, SRAI_W_DESC, Requires<[HasMSA]>;
 def SRAI_D : SRAI_D_ENC, SRAI_D_DESC, Requires<[HasMSA]>;
 
+def SRAR_B : SRAR_B_ENC, SRAR_B_DESC, Requires<[HasMSA]>;
+def SRAR_H : SRAR_H_ENC, SRAR_H_DESC, Requires<[HasMSA]>;
+def SRAR_W : SRAR_W_ENC, SRAR_W_DESC, Requires<[HasMSA]>;
+def SRAR_D : SRAR_D_ENC, SRAR_D_DESC, Requires<[HasMSA]>;
+
+def SRARI_B : SRARI_B_ENC, SRARI_B_DESC, Requires<[HasMSA]>;
+def SRARI_H : SRARI_H_ENC, SRARI_H_DESC, Requires<[HasMSA]>;
+def SRARI_W : SRARI_W_ENC, SRARI_W_DESC, Requires<[HasMSA]>;
+def SRARI_D : SRARI_D_ENC, SRARI_D_DESC, Requires<[HasMSA]>;
+
 def SRL_B : SRL_B_ENC, SRL_B_DESC, Requires<[HasMSA]>;
 def SRL_H : SRL_H_ENC, SRL_H_DESC, Requires<[HasMSA]>;
 def SRL_W : SRL_W_ENC, SRL_W_DESC, Requires<[HasMSA]>;
@@ -2491,6 +2794,16 @@ def SRLI_H : SRLI_H_ENC, SRLI_H_DESC, Requires<[HasMSA]>;
 def SRLI_W : SRLI_W_ENC, SRLI_W_DESC, Requires<[HasMSA]>;
 def SRLI_D : SRLI_D_ENC, SRLI_D_DESC, Requires<[HasMSA]>;
 
+def SRLR_B : SRLR_B_ENC, SRLR_B_DESC, Requires<[HasMSA]>;
+def SRLR_H : SRLR_H_ENC, SRLR_H_DESC, Requires<[HasMSA]>;
+def SRLR_W : SRLR_W_ENC, SRLR_W_DESC, Requires<[HasMSA]>;
+def SRLR_D : SRLR_D_ENC, SRLR_D_DESC, Requires<[HasMSA]>;
+
+def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC, Requires<[HasMSA]>;
+def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC, Requires<[HasMSA]>;
+def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC, Requires<[HasMSA]>;
+def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC, Requires<[HasMSA]>;
+
 def ST_B: ST_B_ENC, ST_B_DESC, Requires<[HasMSA]>;
 def ST_H: ST_H_ENC, ST_H_DESC, Requires<[HasMSA]>;
 def ST_W: ST_W_ENC, ST_W_DESC, Requires<[HasMSA]>;