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authorJohnny Chen <johnny.chen@apple.com>2011-04-07 01:37:34 +0000
committerJohnny Chen <johnny.chen@apple.com>2011-04-07 01:37:34 +0000
commitf16f4e09ec28fe2de13a1bcda391d7d16a368e3a (patch)
treecfcc3338e26c4a0b8e0db6a8c991998291d6e38f /lib/Target
parent0e382192c1a7750a157e470f749645ac2266d317 (diff)
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Sanity check MSRi for invalid mask values and reject it as invalid.
rdar://problem/9246844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 48a748b..bc0ba92 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -836,6 +836,11 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// MSRi take a mask, followed by one so_imm operand. The mask contains the
// R Bit in bit 4, and the special register fields in bits 3-0.
if (Opcode == ARM::MSRi) {
+ // A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
+ // The hints instructions have more specific encodings, so if mask == 0,
+ // we should reject this as an invalid instruction.
+ if (slice(insn, 19, 16) == 0)
+ return false;
MI.addOperand(MCOperand::CreateImm(slice(insn, 22, 22) << 4 /* R Bit */ |
slice(insn, 19, 16) /* Special Reg */ ));
// SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.