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authorVincent Lejeune <vljn@ovi.com>2013-10-13 17:56:10 +0000
committerVincent Lejeune <vljn@ovi.com>2013-10-13 17:56:10 +0000
commitf2b3a569ae25dbba264cef93602b4147d2a723d6 (patch)
tree857095c64034e715e31ce2dcd5e14b7b1af4c5e8 /lib/Target
parent91ec4b0cac7a7476a9d30d6f1adbf218ee6673a0 (diff)
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R600: Use masked read sel for texture instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192554 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r--lib/Target/R600/R600ISelLowering.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp
index 81a28be..3c2e388 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -1379,6 +1379,11 @@ CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry,
};
for (unsigned i = 0; i < 4; i++) {
+ if (NewBldVec[i].getOpcode() == ISD::UNDEF)
+ // We mask write here to teach later passes that the ith element of this
+ // vector is undef. Thus we can use it to reduce 128 bits reg usage,
+ // break false dependencies and additionnaly make assembly easier to read.
+ RemapSwizzle[i] = 7; // SEL_MASK_WRITE
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(NewBldVec[i])) {
if (C->isZero()) {
RemapSwizzle[i] = 4; // SEL_0